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1. 发明申请

US20130282783A1 Systems and Methods for a Floating-Point Multiplication and Accumulation Unit Using a Partial-Product Multiplier in Digital Signal Processors 有权
标题翻译：使用数字信号处理器中的部分乘积乘积的浮点乘积和累积单元的系统和方法
公开(公告)号：US20130282783A1
公开(公告)日：2013-10-24
申请号：US13455064
申请日：2012-04-24
申请人： Zhihong Li , Tong Sun , Zhikun Cheng
发明人： Zhihong Li , Tong Sun , Zhikun Cheng
IPC分类号： G06F7/487 , G06F7/485
CPC分类号： G06F7/5443 , G06F7/4812 , G06F7/483
摘要： An embodiment of an apparatus performs a floating-point multiply-add process on a first multiplicand, a second multiplicand, and an addend. A leading 0 bit is added to a mantissa of the first multiplicand to form an expanded first mantissa, and a partial-product multiplication is performed on the expanded first mantissa and a mantissa of the second multiplicand to produce partial-product sum and a partial-product carry mantissas. Leading bits of the partial-product sum and carry mantissas are changed to 0 bits if they are both 1 bits, and the partial-product sum and the partial-product carry are shifted right according to an exponent difference of a product of the first multiplicand and the second multiplicand. Otherwise both the partial-product sum and carry mantissas are arithmetically shifted right according to the exponent difference. The first and second multiplicands and the addend can be complex numbers.
摘要翻译：装置的实施例对第一被乘数，第二被乘数和加数执行浮点乘法加法处理。前导0比特被添加到第一被乘数的尾数以形成扩展的第一尾数，并且对扩展的第一尾数执行部分乘积和第二被乘数的尾数以产生部分乘积和部分乘积，产品携带尾数。如果它们都是1位，则部分积和和携带尾数的前导位被改变为0位，并且部分积和和部分乘积进位根据第一被乘数的乘积的指数差和第二被乘数。否则，根据指数差异，部分乘积和携带尾数都被算术右移。第一和第二被乘数和加数可以是复数。

2. 发明授权

US08930433B2 Systems and methods for a floating-point multiplication and accumulation unit using a partial-product multiplier in digital signal processors 有权
标题翻译：在数字信号处理器中使用部分乘积的浮点乘法和累加单元的系统和方法
公开(公告)号：US08930433B2
公开(公告)日：2015-01-06
申请号：US13455064
申请日：2012-04-24
申请人： Zhihong Li , Tong Sun , Zhikun Cheng
发明人： Zhihong Li , Tong Sun , Zhikun Cheng
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F7/4812 , G06F7/483
摘要： An embodiment of an apparatus performs a floating-point multiply-add process on a first multiplicand, a second multiplicand, and an addend. A leading 0 bit is added to a mantissa of the first multiplicand to form an expanded first mantissa, and a partial-product multiplication is performed on the expanded first mantissa and a mantissa of the second multiplicand to produce partial-product sum and a partial-product carry mantissas. Leading bits of the partial-product sum and carry mantissas are changed to 0 bits if they are both 1 bits, and the partial-product sum and the partial-product carry are shifted right according to an exponent difference of a product of the first multiplicand and the second multiplicand. Otherwise both the partial-product sum and carry mantissas are arithmetically shifted right according to the exponent difference. The first and second multiplicands and the addend can be complex numbers.
摘要翻译：装置的实施例对第一被乘数，第二被乘数和加数执行浮点乘法加法处理。前导0位被添加到第一被乘数的尾数以形成扩展的第一尾数，并且对扩展的第一尾数进行部分乘积和第二被乘数的尾数以产生部分乘积和部分乘法，产品携带尾数。如果它们都是1位，则部分积和和携带尾数的前导位被改变为0位，并且部分积和和部分乘积进位根据第一被乘数的乘积的指数差和第二被乘数。否则，根据指数差异，部分乘积和携带尾数都被算术右移。第一和第二被乘数和加数可以是复数。

3. 发明授权

US09274750B2 System and method for signal processing in digital signal processors 有权
标题翻译：数字信号处理器信号处理系统和方法
公开(公告)号：US09274750B2
公开(公告)日：2016-03-01
申请号：US13452690
申请日：2012-04-20
申请人： Tong Sun , Weizhong Chen , Zhikun Cheng , Yuanbin Guo
发明人： Tong Sun , Weizhong Chen , Zhikun Cheng , Yuanbin Guo
IPC分类号： G06F7/48 , G06F7/483 , G06F7/544
CPC分类号： G06F7/4806 , G06F7/483 , G06F7/5443
摘要： An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.
摘要翻译：提供了一种用于浮点复数乘法的数字计算的方法和相关装置的实施例。该方法包括接收输入加数，第一产品和第二产品。输入加法，第一产品和第二产品分别具有尾数和指数。该方法包括以输入加数，第一乘积和第二乘积的较小指数移动两者的尾数，使其与输入加法器，第一乘积和第二乘积的最大指数的尾数对齐，并添加对齐的输入加数，对齐的第一个产品和对齐的第二个产品。

4. 发明申请

US20130282778A1 System and Method for Signal Processing in Digital Signal Processors 有权
标题翻译：数字信号处理器信号处理系统与方法
公开(公告)号：US20130282778A1
公开(公告)日：2013-10-24
申请号：US13452690
申请日：2012-04-20
申请人： Tong Sun , Weizhong Chen , Zhikun Cheng , Yuanbin Guo
发明人： Tong Sun , Weizhong Chen , Zhikun Cheng , Yuanbin Guo
IPC分类号： G06F7/483 , G06F17/10 , G06F7/499 , G06F5/01
CPC分类号： G06F7/4806 , G06F7/483 , G06F7/5443
摘要： An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.
摘要翻译：提供了一种用于浮点复数乘法的数字计算的方法和相关装置的实施例。该方法包括接收输入加数，第一产品和第二产品。输入加法，第一产品和第二产品分别具有尾数和指数。该方法包括以输入加数，第一乘积和第二乘积的较小指数移动两者的尾数，使其与输入加法器，第一乘积和第二乘积的最大指数的尾数对齐，并添加对齐的输入加数，对齐的第一个产品和对齐的第二个产品。

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