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1. 发明授权

US08426288B2 Method for improving capacitance uniformity in a MIM device 有权
标题翻译：用于改善MIM器件中的电容均匀性的方法
公开(公告)号：US08426288B2
公开(公告)日：2013-04-23
申请号：US13339406
申请日：2011-12-29
申请人： Qiang Xu , Wenguang Zhang , Chunsheng Zheng , Yuwen Chen
发明人： Qiang Xu , Wenguang Zhang , Chunsheng Zheng , Yuwen Chen
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , C23C16/345 , C23C16/45523 , C23C16/505 , C23C16/56
摘要： A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.
摘要翻译：主要用于提高MIM器件内的薄膜均匀性的MIM器件中的电容均匀性的改善方法包括8个步骤，并且步骤S2的步骤S6可根据需要重复多次。根据本发明的MIM器件中的电容均匀性的提高方法，通过基于当前PECVD的多次沉积/等离子体处理，去除薄膜中的一定量的缺陷，并且沉积的薄膜膜增加，从而提高了薄膜的湿蚀刻速度的均匀性，并且进一步提高了MIM器件中的电容均匀性。

2. 发明申请

US20120276820A1 Method for Adjusting Metal Polishing Rate and Reducing Defects Arisen in a Polishing Process 审中-公开
标题翻译：调整金属抛光速率和减少抛光过程中出现的缺陷的方法
公开(公告)号：US20120276820A1
公开(公告)日：2012-11-01
申请号：US13339538
申请日：2011-12-29
申请人： Shoulong Zhang , Yingying Bai , Yuwen Chen
发明人： Shoulong Zhang , Yingying Bai , Yuwen Chen
IPC分类号： B24B1/00
CPC分类号： H01L21/7684 , B24B37/046 , B24B37/22 , B24B37/24 , H01L21/32125
摘要： The invention discloses a method for adjusting metal polishing rate and reducing defects arisen in a polishing process, in which a electric conduction system is additionally provided to a polishing apparatus to electrify the polishing fluid; in the polishing process, the polishing fluid flows through the polishing pad and the wafer to be polished, such that the polished metal surface of the wafer is electrically charged so as to control the oxidation of the polished metal surface of the wafer. The invention has solved the problem that the dishing and erosion defects are prone to be formed in the existing polishing process, the potential of the polishing fluid is changed by means of the additional electric conduction system and thus the polishing rate of the polished metal is controlled so as to reduce the dishing and erosion defects occurred in the polishing process.
摘要翻译：本发明公开了一种用于调整金属抛光速率并减少在抛光工艺中产生的缺陷的方法，其中将电传导系统附加地提供给抛光装置以使抛光液带电; 在抛光过程中，抛光液流过待研磨的抛光垫和晶片，使得抛光的晶片的金属表面被带电，以便控制晶片抛光的金属表面的氧化。本发明解决了在现有的抛光工艺中容易形成凹陷和侵蚀缺陷的问题，通过附加的导电系统改变抛光液的电位，从而控制抛光金属的抛光速度以减少抛光过程中发生的凹陷和侵蚀缺陷。

3. 发明申请

US20130109186A1 METHOD OF FORMING SEMICONDUCTOR DEVICES USING SMT 审中-公开
标题翻译：使用SMT形成半导体器件的方法
公开(公告)号：US20130109186A1
公开(公告)日：2013-05-02
申请号：US13662277
申请日：2012-10-26
申请人： Wenguang ZHANG , Qiang XU , Chunsheng Zheng , Lingzhi Xu , Yuwen Chen
发明人： Wenguang ZHANG , Qiang XU , Chunsheng Zheng , Lingzhi Xu , Yuwen Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/3105 , H01L21/823807 , H01L29/7843 , H01L29/7847
摘要： The present invention provides a method of forming semiconductor devices using SMT. The method comprises providing a substrate; depositing an SiO2 buffer film and a low tensile stress SiN film on the substrate; applying photoresist over the low tensile stress SiN film and exposing the low tensile stress SiN film on the NMOS region through photoresist exposure; applying UV radiation to the exposed low tensile stress SiN film; removing some hydrogen in the low tensile stress SiN film on the NMOS region and removing photoresist over the PMOS region; performing a rapid thermal annealing process to induce tensile stress in the NMOS channel region; and removing the SiN film and the SiO2 buffer film. According to the method of forming semiconductor devices using SMT of the present invention, the conventional SMT is greatly simplified.
摘要翻译：本发明提供使用SMT形成半导体器件的方法。该方法包括提供基底; 在衬底上沉积SiO 2缓冲膜和低拉伸应力SiN膜; 在低拉伸应力SiN膜上施加光致抗蚀剂，并通过光致抗蚀剂曝光使NMOS区域上的低拉伸应力SiN膜暴露; 对暴露的低拉伸应力SiN膜施加紫外线辐射; 去除NMOS区域上的低拉伸应力SiN膜中的一些氢，并去除PMOS区域上的光致抗蚀剂; 执行快速热退火工艺以在NMOS沟道区域中引起拉伸应力; 并且去除SiN膜和SiO 2缓冲膜。根据使用本发明的使用SMT的半导体器件的方法，传统的SMT被大大简化。

4. 发明申请

US20130065385A1 METHOD FOR PREPARING SPACER TO REDUCE COUPLING INTERFERENCE IN MOSFET 审中-公开
标题翻译：用于制备间隔器以减少MOSFET中的耦合干扰的方法
公开(公告)号：US20130065385A1
公开(公告)日：2013-03-14
申请号：US13339422
申请日：2011-12-29
申请人： Xiaolu HUANG , Chaos ZHANG , Yuwen CHEN
发明人： Xiaolu HUANG , Chaos ZHANG , Yuwen CHEN
IPC分类号： H01L21/28
CPC分类号： H01L29/4983 , H01L29/7833
摘要： The present invention provides a method for preparing spacer to reduce coupling interference in MOSFET, which includes the steps of: forming a gate oxide layer on the semiconductor substrate; forming a gate on the gate oxide layer; and depositing a low-K dielectric material on the gate and the semiconductor substrate, and doping with carbon during deposition to form a carbon-containing low-K dielectric layer and then forming the spacer by an etching process.
摘要翻译：本发明提供一种用于制备间隔物以减少MOSFET中的耦合干扰的方法，其包括以下步骤：在半导体衬底上形成栅极氧化层; 在栅极氧化层上形成栅极; 以及在栅极和半导体衬底上沉积低K电介质材料，并在沉积期间掺杂碳以形成含碳低K电介质层，然后通过蚀刻工艺形成间隔物。

5. 发明申请

US20120302038A1 METHOD FOR PREPARING A SHALLOW TRENCH ISOLATION STRUCTURE WITH THE STRESS OF ITS ISOLATION OXIDE BEING TUNED BY ION IMPLANTATION 审中-公开
标题翻译：用于通过离子植入调节其分离氧化物的应力的方法制备浅层分离结构
公开(公告)号：US20120302038A1
公开(公告)日：2012-11-29
申请号：US13339404
申请日：2011-12-29
申请人： Chunsheng ZHENG , Wenguang ZHANG , Qiang XU , Yuwen CHEN
发明人： Chunsheng ZHENG , Wenguang ZHANG , Qiang XU , Yuwen CHEN
IPC分类号： H01L21/302
CPC分类号： H01L21/76237 , H01L21/31155 , H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： A method for preparing a shallow trench isolation structure with the stress of its isolation oxide being tuned by ion implantation comprises: step a: forming a protective layer on a semiconductor substrate; step b: forming trenches for isolating PMOS active regions and NMOS active regions on the semiconductor substrate and the protective layer; step c: forming a filling material layer in the trenches, so that the trenches are fully filled with the filling material layer to form shallow trench isolation structures. The advantageous is that, as for a device where a HARP process is applied to its shallow trench isolation, the stress in the STI can be tuned so as to be changed from tensile stress into compressive stress by performing ion implantation to the STI around the PMOS, therefore the stress state of the PMOS channel region may be changed and the performance thereof is improved.
摘要翻译：通过离子注入来调节其隔离氧化物的应力的浅沟槽隔离结构的制备方法包括：步骤a：在半导体衬底上形成保护层; 步骤b：形成用于隔离半导体衬底和保护层上的PMOS有源区和NMOS有源区的沟槽; 步骤c：在沟槽中形成填充材料层，使得沟槽被填充材料层完全填充以形成浅沟槽隔离结构。有利的是，对于将HARP工艺应用于其浅沟槽隔离的器件，可以调节STI中的应力，以便通过对PMOS周围的STI进行离子注入，将其从拉伸应力变为压应力因此，可以改变PMOS沟道区的应力状态并提高其性能。

6. 发明授权

US08507355B2 Manufacturing method of a high performance metal-oxide-metal 有权
标题翻译：高性能金属氧化物金属的制造方法
公开(公告)号：US08507355B2
公开(公告)日：2013-08-13
申请号：US13339593
申请日：2011-12-29
申请人： Youcun Hu , Lei Li , Chaos Zhang , Feng Ji , Yuwen Chen
发明人： Youcun Hu , Lei Li , Chaos Zhang , Feng Ji , Yuwen Chen
IPC分类号： H01L21/20
CPC分类号： H01L28/60 , H01L21/76802 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing high performance metal-oxide-metal capacitor device that resolves problems with implementing high capacitance in the metal-oxide-metal region by filling with a low-k material both in the metal-oxide-metal region and the metal interconnection region, utilizing performing selective photolithography and etching of the first dielectric layer to define metal-oxide-metal (MOM for short) region, and filling the MOM region with high dielectric constant (high-k) material to realize a high performance MOM capacitor.
摘要翻译：一种制造高性能金属 - 氧化物 - 金属电容器器件的方法，其通过在金属氧化物金属区域和金属互连区域中填充低k材料来解决在金属 - 氧化物 - 金属区域中实现高电容的问题利用执行选择性光刻和蚀刻第一介电层以限定金属氧化物金属（MOM）区域，并且填充具有高介电常数（高k）材料的MOM区域，以实现高性能MOM电容器。

7. 发明申请

US20130049119A1 MULTI-WORKING VOLTAGES CMOS DEVICE WITH SINGLE GATE OXIDE LAYER THICKNESS AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有单栅氧化层厚度及其制造方法的多工作电压CMOS器件
公开(公告)号：US20130049119A1
公开(公告)日：2013-02-28
申请号：US13339438
申请日：2011-12-29
申请人： Xiaolu HUANG , Gang MAO , Yuwen CHEN , Xinyun XIE
发明人： Xiaolu HUANG , Gang MAO , Yuwen CHEN , Xinyun XIE
IPC分类号： H01L27/092 , H01L27/12 , H01L21/86 , H01L21/8238
CPC分类号： H01L21/823857
摘要： The present invention provides a multi-working voltages CMOS device with single gate oxide layer thickness, gate work functions of CMOS transistors are regulated by implanting ions with different work functions into metal oxide dielectric material layers of the CMOS transistors, thus to realize different flat-band voltages under the condition of single dielectric layer thickness, and realize a multi-working voltages CMOS structure under the condition of single dielectric layer thickness. The present invention overcomes the process complexity of multiple kinds of gate dielectric layer thicknesses needed by traditional multi-working voltages CMOS, simplifies the CMOS process, makes the manufacturing procedure simple and easy to execute, reduces the preparation cost and is suitable for industrial production.
摘要翻译：本发明提供具有单栅极氧化层厚度的多工作电压CMOS器件，通过将具有不同功函数的离子注入到CMOS晶体管的金属氧化物介电材料层中来调节CMOS晶体管的栅极功能，从而实现不同的平面 - 在单介电层厚度的条件下，实现多层电压CMOS结构，在单介电层厚度条件下实现多工作电压CMOS结构。本发明克服了传统多工作电压CMOS所需的多种栅极电介质层的工艺复杂性，简化了CMOS工艺，使制造工艺简单易行，降低了制备成本，适合工业生产。

8. 发明申请

US20130020652A1 METHOD FOR SUPPRESSING SHORT CHANNEL EFFECT OF CMOS DEVICE 审中-公开
标题翻译：抑制CMOS器件短路通道效应的方法
公开(公告)号：US20130020652A1
公开(公告)日：2013-01-24
申请号：US13339429
申请日：2011-12-29
申请人： Xiaolu HUANG , Gang MAO , Yuwen CHEN , Tzuyin CHIU
发明人： Xiaolu HUANG , Gang MAO , Yuwen CHEN , Tzuyin CHIU
IPC分类号： H01L21/266 , H01L27/092
CPC分类号： H01L21/823807 , H01L21/26586 , H01L21/823828 , H01L29/1083 , H01L29/51 , H01L29/66537 , H01L29/66545 , H01L29/66606
摘要： A method for manufacturing a gate-last high-K CMOS structure comprising a first transistor and a second transistor, which is formed in a Si substrate includes: implanting acceptor impurity into a gate recess of the first transistor to form a first buried-layer heavily doping region under a channel of the first transistor; and implanting donor impurity into a gate recess of the second transistor to form a second buried-layer heavily doping region under a channel of the second transistor.
摘要翻译：一种形成在Si衬底中的包括第一晶体管和第二晶体管的栅极 - 末端高K CMOS结构的制造方法，包括：将受主杂质注入到第一晶体管的栅极凹槽中以形成第一掩埋层第一晶体管的沟道下方的掺杂区域; 以及将施主杂质注入到所述第二晶体管的栅极凹槽中，以在所述第二晶体管的沟道下形成第二掩埋层重掺杂区。

9. 发明申请

US20120322256A1 Manufacturing Method of a High Performance Metal-Oxide-Metal 有权
标题翻译：高性能金属氧化物金属的制造方法
公开(公告)号：US20120322256A1
公开(公告)日：2012-12-20
申请号：US13339593
申请日：2011-12-29
申请人： Youcun Hu , Lei Li , Chaos Zhang , Feng Ji , Yuwen Chen
发明人： Youcun Hu , Lei Li , Chaos Zhang , Feng Ji , Yuwen Chen
IPC分类号： H01L21/768
CPC分类号： H01L28/60 , H01L21/76802 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： The manufacturing method of the high performance metal-oxide-metal according to the present invention resolves the problems of implementing high capacitance in the metal-oxide-metal region by the steps of filling with a low-k material both in the metal-oxide-metal region and the metal interconnection region, utilizing performing selective photolithography and etching of the first dielectric layer to define metal-oxide-metal (MOM for short) region, and fulfilling the MOM region with high dielectric constant (high-k) material to realize a high performance MOM capacitor. Using the present method, high-k material and low-k material within the same film layer are realized. High-k material region is used as MOM to achieve high capacitor c, thereby reducing the area used by chips and further improving the electrics performance.
摘要翻译：根据本发明的高性能金属氧化物金属的制造方法通过以下步骤来解决在金属氧化物 - 金属区域中实现高电容的问题：在金属氧化物 - 金属 - 金属区域中填充低k材料，金属区域和金属互连区域，利用第一介电层的选择性光刻和蚀刻来限定金属氧化物金属（MOM）区域，并实现具有高介电常数（高k）材料的MOM区域，以实现高性能MOM电容器。使用本方法，实现了在相同膜层内的高k材料和低k材料。将高k材料区域用作MOM以实现高电容器c，从而减小芯片使用的面积并进一步提高电气性能。

10. 发明申请

US20120322222A1 METHOD FOR IMPROVING CAPACITANCE UNIFORMITY IN A MIM DEVICE 有权
标题翻译：用于改善MIM器件中的电容均匀性的方法
公开(公告)号：US20120322222A1
公开(公告)日：2012-12-20
申请号：US13339406
申请日：2011-12-29
申请人： Qiang XU , Wenguang ZHANG , Chunsheng ZHENG , Yuwen CHEN
发明人： Qiang XU , Wenguang ZHANG , Chunsheng ZHENG , Yuwen CHEN
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , C23C16/345 , C23C16/45523 , C23C16/505 , C23C16/56
摘要： A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S2-step S6 may be repeated for several times as needed. According to the method for improving capacitance uniformity in a MIM device of the present invention, a certain quantity of defects in the thin film are removed by means of several times of deposition/plasma processes based on the current PECVD, and uniformity of the deposited thin film is increased, thereby improving uniformity in wet etching rate of the thin film and further improving capacitance uniformity in the MIM device.
摘要翻译：主要用于提高MIM器件内的薄膜均匀性的MIM器件中的电容均匀性的改善方法包括8个步骤，并且步骤S2的步骤S6可根据需要重复多次。根据本发明的MIM器件中的电容均匀性的提高方法，通过基于当前PECVD的多次沉积/等离子体处理，去除薄膜中的一定量的缺陷，并且沉积的薄膜膜增加，从而提高了薄膜的湿蚀刻速度的均匀性，并且进一步提高了MIM器件中的电容均匀性。

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