专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20150380139A1 POSITIONING COMPONENT FOR AN ELECTRONIC DEVICE 审中-公开
标题翻译：电子设备的定位组件
公开(公告)号：US20150380139A1
公开(公告)日：2015-12-31
申请号：US14763975
申请日：2013-06-21
申请人： Yung-Lung HSU , SUPERMAX CO., LTD.
发明人： Yung-Lung HSU
IPC分类号： H01F7/02
CPC分类号： H01F7/0252 , G06F1/1628 , H04M1/04
摘要： A set of positioning component for fast positioning of a portable electronic device taking advantage of the characteristics of magnetic adsorption and mutual ejecting, the component includes a housing with a first magnetic unit having multi-poles to be fixed on the back of the electronic device; and includes a supporting piece with a second magnetic unit having multi-poles, the multi-poles of the second magnetic unit are provided with contrary magnetic polarities relative to that of the first magnetic unit, so that the multi-poles of the first magnetic unit can be adsorbed onto the second magnetic unit, and the housing can be strongly adsorbed and positioned on the supporting piece from a special angular direction; when the housing does bias rotation for an angle, the first magnetic unit and the second magnetic unit reject and separate mutually with each other to render the housing to be fast detached.
摘要翻译：利用磁吸附和相互喷射的特点，便携式电子设备的快速定位的一组定位组件，该组件包括具有固定在电子设备背面上的具有多极的第一磁性单元的外壳; 并且包括具有多极的第二磁性单元的支撑件，第二磁性单元的多极相对于第一磁性单元的多极具有相反的磁极，使得第一磁性单元的多极可以吸附到第二磁性单元上，并且可以从特定的角度方向将壳体强力吸附并定位在支撑件上; 当壳体以一定角度偏置旋转时，第一磁性单元和第二磁性单元彼此相互排斥和分离，使壳体快速分离。

2. 发明授权

US6069063A Method to form polysilicon resistors shielded from hydrogen intrusion 有权
标题翻译：形成多晶硅电阻屏蔽氢入侵的方法
公开(公告)号：US6069063A
公开(公告)日：2000-05-30
申请号：US283841
申请日：1999-04-01
申请人： Juin-Jie Chang , Shih-Chi Lin , Yen-Ming Chen , Yung-Lung Hsu
发明人： Juin-Jie Chang , Shih-Chi Lin , Yen-Ming Chen , Yung-Lung Hsu
IPC分类号： H01L21/02 , H01L21/3115 , H01L21/314 , H01L21/425
CPC分类号： H01L28/20 , H01L21/31155 , H01L21/3144
摘要： A method to form polysilicon resistors shielded from hydrogen intrusion is described. A semiconductor substrate is provided. Field oxide isolation regions are provided overlying the substrate. A polysilicon layer is deposited overlying the field oxide regions and the substrate. The polysilicon layer is etched away where it is not covered by a mask to form a polysilicon resistor. An interlevel dielectric layer is deposited overlying the polysilicon resistor. Nitrogen ions are implanted into the interlevel dielectric layer. The interlevel dielectric layer is annealed to form a silicon oxynitride shield layer in the interlevel dielectric layer. Contact openings are etched through the interlevel dielectric layer to the polysilicon resistor. The contact openings are filled with a metal layer. The metal layer is patterned. The patterned metal layer is covered with a passivation layer wherein the passivation layer contains hydrogen atoms and wherein the silicon oxynitride shield layer prevents hydrogen atoms from penetrating the polysilicon resistor. The integrated circuit is completed.
摘要翻译：描述了形成多晶硅电阻器防止氢侵入的方法。提供半导体衬底。场氧化物隔离区设置在衬底上。叠加在场氧化物区域和衬底上的多晶硅层。多晶硅层被蚀刻掉，其未被掩模覆盖以形成多晶硅电阻器。沉积层叠介质层覆盖多晶硅电阻器。将氮离子注入到层间电介质层中。对层间电介质层进行退火，在层间电介质层中形成氮氧化硅屏蔽层。接触开口通过层间介质层蚀刻到多晶硅电阻器。接触开口填充有金属层。金属层被图案化。图案化的金属层被钝化层覆盖，其中钝化层含有氢原子，并且其中氮氧化硅屏蔽层防止氢原子穿透多晶硅电阻器。集成电路完成。

3. 发明授权

US06939726B2 Via array monitor and method of monitoring induced electrical charging 失效
公开(公告)号：US06939726B2
公开(公告)日：2005-09-06
申请号：US10634005
申请日：2003-08-04
申请人： Yung-Lung Hsu , James Wu
发明人： Yung-Lung Hsu , James Wu
IPC分类号： H01L21/66 , H01L23/544 , G01R31/26 , H01L21/4763
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/3011 , Y10S438/926
摘要： An electrical monitor comprising a via array and method for determining and reducing an electrically charged state of a semiconductor process wafer the method including providing a metal filled via array including a plurality of interspersed electrically isolated dummy metal portions to form a via array monitor; exposing the semiconductor process wafer including the via array monitor to an electrical charge altering process including to produce an electrically charged state over at least a portion of the semiconductor wafer; carrying out electrical measurements of the via array monitor to determine a level of the electrically charged state; and, carrying out an electrically charge neutralizing process to reduce a level of the electrically charged state to a predetermined acceptable level prior to carrying out a subsequent process.

4. 发明授权

US06340833B1 Integrated circuit polysilicon resistor having a silicide extension to achieve 100 % metal shielding from hydrogen intrusion 有权
标题翻译：具有硅化物延伸的集成电路多晶硅电阻器，以实现100％金属屏蔽氢侵入
公开(公告)号：US06340833B1
公开(公告)日：2002-01-22
申请号：US09693502
申请日：2000-10-23
申请人： Ruey-Hsin Liu , Jun-Lin Tsai , Yung-Lung Hsu
发明人： Ruey-Hsin Liu , Jun-Lin Tsai , Yung-Lung Hsu
IPC分类号： H01L2900
CPC分类号： H01L28/20 , H01L27/0802
摘要： A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor. The metal is also patterned to form a metal shield over the resistor to prevent hydrogen diffusion into the resistor. In this invention the spacing between the metal portions contacting the ends of the resistor is aligned over the silicide on the resistor to provide 100% shielding from hydrogen diffusion into the resistor.
摘要翻译：通过使用防止氢进入电阻器的硅化物层来实现稳定的高价值多晶硅电阻器。电阻器也可以集成到自对准硅化物工艺中，用于制造FET而不增加工艺复杂性。图案化具有帽氧化物的多晶硅层以形成FET栅电极和多晶硅电阻器。形成了用于FET的轻掺杂源极/漏极，绝缘侧壁间隔物和源极/漏极接触。盖帽氧化物被图案化以暴露电阻器的一端，并且帽状氧化物从栅电极移除。沉积和退火难熔金属以形成硅化物FET并同时在电阻器的末端形成硅化物。未反应的金属被蚀刻。沉积层间电介质层，并且在电阻器的两端形成与金属插塞的接触孔。沉积金属以形成第一级金属互连，其也提供与电阻器两端的接触。金属也被图案化以在电阻器上形成金属屏蔽，以防止氢扩散到电阻器中。在本发明中，接触电阻器端部的金属部分之间的间隔在电阻器上的硅化物上排列，以提供100％的阻挡氢扩散到电阻器中的屏蔽。

5. 发明授权

US06271068B1 Method for making improved polysilicon emitters for bipolar transistors on BiCMOS integrated circuits 有权
标题翻译：用于在BiCMOS集成电路上制造用于双极晶体管的改进的多晶硅发射极的方法
公开(公告)号：US06271068B1
公开(公告)日：2001-08-07
申请号：US09755279
申请日：2001-01-08
申请人： Yung-Lung Hsu , Ruey-Hsin Liou
发明人： Yung-Lung Hsu , Ruey-Hsin Liou
IPC分类号： H01L218238
CPC分类号： H01L29/66272 , H01L21/8249
摘要： A method for making an improved polysilicon emitter for a bipolar transistor in a BiCMOS integrated circuit is achieved. The method uses a novel stacked undoped amorphous silicon layer and a doped polysilicon layer. The polysilicon layer is doped by ion implantation while the amorphous silicon layer remains undoped. The stacked layer is patterned to form a polysilicon emitter source over the bipolar transistor, while concurrently forming gate electrodes for the FETs. The undoped amorphous silicon layer retards the diffusion from the doped polysilicon to provide a shallower emitter junction during subsequent thermal processing. At a later step a rapid thermal anneal (RTA) is carried out in which the amorphous silicon layer provides better control of the diffused emitter depth (junction) while concurrently activating the implant dopant in the FET source/drain areas. The better control of the shallow emitter depth over the conventional doped polysilicon emitter results in a smaller standard deviation of the current gain. Also the collector-to-emitter breakdown voltage is increased, and the reduced junction capacitance increases the cutoff frequency.
摘要翻译：实现了BiCMOS集成电路中用于双极晶体管的改进的多晶硅发射极的方法。该方法使用新颖的堆叠未掺杂非晶硅层和掺杂多晶硅层。多晶硅层通过离子注入掺杂，而非晶硅层保持未掺杂。图案化堆叠层以在双极晶体管上形成多晶硅发射极源，同时形成用于FET的栅电极。未掺杂的非晶硅层延迟了掺杂多晶硅的扩散，从而在随后的热处理期间提供较浅的发射极结。在稍后的步骤中，执行快速热退火（RTA），其中非晶硅层在扩散的发射极深度（结）处提供更好的控制，同时激活FET源极/漏极区域中的注入掺杂剂。在常规掺杂多晶硅发射器上对浅发射极深度的更好控制导致电流增益的较小的标准偏差。此外，集电极到发射极的击穿电压增加，并且减小的结电容增加了截止频率。

6. 发明申请

US20050032253A1 Via array monitor and method of monitoring induced electrical charging 失效
标题翻译：通过阵列监视器和监控感应充电的方法
公开(公告)号：US20050032253A1
公开(公告)日：2005-02-10
申请号：US10634005
申请日：2003-08-04
申请人： Yung-Lung Hsu , James Wu
发明人： Yung-Lung Hsu , James Wu
IPC分类号： H01L21/66 , H01L23/544 , H01L21/4763 , H01L23/58
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/3011 , Y10S438/926
摘要： An electrical monitor comprising a via array and method for determining and reducing an electrically charged state of a semiconductor process wafer the method including providing a metal filled via array including a plurality of interspersed electrically isolated dummy metal portions to form a via array monitor; exposing the semiconductor process wafer including the via array monitor to an electrical charge altering process including to produce an electrically charged state over at least a portion of the semiconductor wafer; carrying out electrical measurements of the via array monitor to determine a level of the electrically charged state; and, carrying out an electrically charge neutralizing process to reduce a level of the electrically charged state to a predetermined acceptable level prior to carrying out a subsequent process.
摘要翻译：一种电监测器，包括用于确定和减少半导体工艺晶片的带电状态的通孔阵列和方法，所述方法包括提供包括多个散置的电隔离的虚设金属部分的金属填充通孔阵列以形成通孔阵列监视器; 将包括通孔阵列监视器的半导体工艺晶片暴露于电荷改变过程，其包括在半导体晶片的至少一部分上产生带电状态; 执行通孔阵列监视器的电气测量以确定带电状态的水平; 并且进行电荷中和处理，以在执行后续处理之前将带电状态的水平降低到预定的可接受水平。

7. 发明授权

US6165861A Integrated circuit polysilicon resistor having a silicide extension to achieve 100% metal shielding from hydrogen intrusion 有权
标题翻译：具有硅化物延伸的集成电路多晶硅电阻器，以实现100％金属屏蔽氢侵入
公开(公告)号：US6165861A
公开(公告)日：2000-12-26
申请号：US152348
申请日：1998-09-14
申请人： Ruey-Hsin Liu , Jun-Lin Tsai , Yung-Lung Hsu
发明人： Ruey-Hsin Liu , Jun-Lin Tsai , Yung-Lung Hsu
IPC分类号： H01L21/02 , H01L27/08 , H01L21/20
CPC分类号： H01L28/20 , H01L27/0802
摘要： A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor. The metal is also patterned to form a metal shield over the resistor to prevent hydrogen diffusion into the resistor. In this invention the spacing between the metal portions contacting the ends of the resistor is aligned over the silicide on the resistor to provide 100% shielding from hydrogen diffusion into the resistor.
摘要翻译：通过使用防止氢进入电阻器的硅化物层来实现稳定的高价值多晶硅电阻器。电阻器也可以集成到自对准硅化物工艺中，用于制造FET而不增加工艺复杂性。图案化具有帽氧化物的多晶硅层以形成FET栅电极和多晶硅电阻器。形成了用于FET的轻掺杂源极/漏极，绝缘侧壁间隔物和源极/漏极接触。盖帽氧化物被图案化以暴露电阻器的一端，并且帽状氧化物从栅电极移除。沉积和退火难熔金属以形成硅化物FET并同时在电阻器的末端形成硅化物。未反应的金属被蚀刻。沉积层间电介质层，并且在电阻器的两端形成与金属插塞的接触孔。沉积金属以形成第一级金属互连，其也提供与电阻器两端的接触。金属也被图案化以在电阻器上形成金属屏蔽，以防止氢扩散到电阻器中。在本发明中，接触电阻器端部的金属部分之间的间隔在电阻器上的硅化物上排列，以提供100％的阻挡氢扩散到电阻器中的屏蔽。

8. 发明授权

US07205167B2 Method to detect photoresist residue on a semiconductor device 有权
标题翻译：检测半导体器件上的光致抗蚀剂残留物的方法
公开(公告)号：US07205167B2
公开(公告)日：2007-04-17
申请号：US10842178
申请日：2004-05-10
申请人： To-Yu Chen , Mei-Yen Li , Yung-Lung Hsu
发明人： To-Yu Chen , Mei-Yen Li , Yung-Lung Hsu
IPC分类号： H01L21/66
CPC分类号： G03F7/70608 , H01L21/0271 , H01L22/24
摘要： A method for detecting photoresist residue during semiconductor device manufacture includes developing photoresist on a surface of a semiconductor device to expose portions of the surface A plurality of etch paths are then partially etched into the surface and inspected to determine their depths.
摘要翻译：在半导体器件制造期间检测光致抗蚀剂残留物的方法包括在半导体器件的表面上显影光致抗蚀剂以暴露部分表面多个蚀刻路径然后被部分蚀刻到表面中并进行检查以确定其深度。

9. 发明授权

US06291306B1 Method of improving the voltage coefficient of resistance of high polysilicon resistors 有权
标题翻译：提高高多晶硅电阻电阻电压系数的方法
公开(公告)号：US06291306B1
公开(公告)日：2001-09-18
申请号：US09357243
申请日：1999-07-19
申请人： Yung-Lung Hsu , Shun-Liang Hsu , Yean-Kuen Fang , Mao-Hsiung Kuo
发明人： Yung-Lung Hsu , Shun-Liang Hsu , Yean-Kuen Fang , Mao-Hsiung Kuo
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L27/0802
摘要： A method of forming a high polysilicon resistor over a dielectric layer, comprising the following steps. A polysilicon resistor over a semiconductor structure is provided. The polysilicon resistor has a doped polysilicon layer having a first voltage coefficient of resistance and grain boundaries having a first trapping density. A to a first level of DC current is provided for a predetermined duration through the doped polysilicon layer to stress the doped polysilicon layer to partially melt the doped polysilicon layer without causing breakdown of the doped polysilicon layer. The to a first level of DC current is removed to allow recrystallization of the melted doped polysilicon layer, whereby the recrystallized doped polysilicon layer has a second voltage coefficient of resistance less than the first voltage coefficient of resistance and grain boundaries having a second trapping density that is less than the first trapping density. This makes the Rs of the polysilicon to be stable and saturated.
摘要翻译：一种在电介质层上形成高多晶硅电阻的方法，包括以下步骤。提供了半导体结构上的多晶硅电阻器。多晶硅电阻器具有掺杂多晶硅层，其具有第一电压电阻系数和具有第一捕获密度的晶界。通过掺杂多晶硅层将A到第一级DC电流提供预定持续时间，以施加掺杂多晶硅层以部分地熔化掺杂多晶硅层而不引起掺杂多晶硅层的击穿。除去第一级直流电流以允许熔融掺杂多晶硅层重结晶，由此再结晶掺杂多晶硅层具有小于第一电压系数电阻的第二电压系数和具有第二陷阱密度的晶界，小于第一个捕获密度。这使得多晶硅的Rs稳定和饱和。

10. 发明申请

US20050250227A1 Method to detect photoresist residue on a semiconductor device 有权
标题翻译：检测半导体器件上的光致抗蚀剂残留物的方法
公开(公告)号：US20050250227A1
公开(公告)日：2005-11-10
申请号：US10842178
申请日：2004-05-10
申请人： To-Yu Chen , Mei-Yen Li , Yung-Lung Hsu
发明人： To-Yu Chen , Mei-Yen Li , Yung-Lung Hsu
IPC分类号： G03F7/20 , H01L21/027 , H01L21/66
CPC分类号： G03F7/70608 , H01L21/0271 , H01L22/24
摘要： A method for detecting photoresist residue during semiconductor device manufacture includes developing photoresist on a surface of a semiconductor device to expose portions of the surface A plurality of etch paths are then partially etched into the surface and inspected to determine their depths.
摘要翻译：在半导体器件制造期间检测光致抗蚀剂残留物的方法包括在半导体器件的表面上显影光致抗蚀剂以暴露部分表面多个蚀刻路径然后被部分蚀刻到表面中并进行检查以确定其深度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式