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1. 发明授权

US5872066A Method of forming inter-metal dielectric layer for WVIA process 失效
标题翻译： WVIA工艺形成金属间介电层的方法
公开(公告)号：US5872066A
公开(公告)日：1999-02-16
申请号：US103860
申请日：1998-06-24
申请人： Cheng-Yu Fang , Kuo-Liang Huang , Ching-Gji Hsu , Yung-Chieh Fan
发明人： Cheng-Yu Fang , Kuo-Liang Huang , Ching-Gji Hsu , Yung-Chieh Fan
IPC分类号： H01L21/316 , H01L21/31 , B05D3/02 , H01L21/469 , H01L21/4763
CPC分类号： H01L21/316
摘要： A method of forming an inter-metal dielectric layer using hydrogen silsesquoxane (HSQ) as one of the dielectric layers. HSQ is a highly fluidic material that has a high gap-filling capacity. Therefore, the desired thickness and uniformity can be obtained in a single coating operation. Furthermore, when the HSQ layer is cured in an atmosphere of gaseous nitrogen, the HSQ layer is able to attain a high degree of planarity. Consequently, there is no need to planarize the dielectric layer before carrying out subsequent operations.
摘要翻译：使用氢硅氧烷（HSQ）作为介电层之一形成金属间介电层的方法。 HSQ是一种高流动性的材料，具有较高的间隙填充能力。因此，可以在单次涂布操作中获得所需的厚度和均匀性。此外，当HSQ层在气态氮气氛中固化时，HSQ层能够获得高度的平坦度。因此，在进行后续操作之前不需要平坦化介质层。

2. 发明授权

US06509243B2 Method for integrating high-voltage device and low-voltage device 失效
标题翻译：高压器件与低压器件集成方法
公开(公告)号：US06509243B2
公开(公告)日：2003-01-21
申请号：US09888909
申请日：2001-06-25
申请人： Yung-Chieh Fan
发明人： Yung-Chieh Fan
IPC分类号： H01L21331
CPC分类号： H01L21/823418 , H01L21/823456 , H01L21/823462 , H01L21/823481
摘要： In a method for integrating a high-voltage device and a low-voltage device, a substrate includes a first isolation region separating a high-voltage device region and a low-voltage device region, a second isolation region formed in a scribe region, and a patterned insulating layer that exposes the first and second isolation regions. A patterned photoresist, formed over the substrate, exposes a portion of the patterned insulating layer in the high-voltage device region and a portion of the second isolation region in the scribe region. A doped region and a trench are respectively formed in the substrate under the exposed portion of the patterned insulating layer and in the exposed portion of the second isolation region. The patterned photoresist and the patterned insulating layer are subsequently removed. First and second gate structures are respectively formed in the high-voltage and low-voltage device regions by using the trench as an alignment mark.
摘要翻译：在高压器件和低电压器件的集成方法中，衬底包括分离高电压器件区域和低电压器件区域的第一隔离区域，形成在划线区域中的第二隔离区域，以及暴露第一和第二隔离区域的图案化绝缘层。形成在衬底上的图案化光致抗蚀剂暴露在高压器件区域中的图案化绝缘层的一部分和划线区域中的第二隔离区域的一部分。掺杂区域和沟槽分别在图案化绝缘层的暴露部分和第二隔离区域的暴露部分中的衬底内形成。随后去除图案化的光致抗蚀剂和图案化的绝缘层。通过使用沟槽作为对准标记，分别在高电压和低电压器件区域中形成第一和第二栅极结构。

3. 发明授权

US6153446A Method for forming a metallic reflecting layer in a semiconductor photodiode 失效
标题翻译：在半导体光电二极管中形成金属反射层的方法
公开(公告)号：US6153446A
公开(公告)日：2000-11-28
申请号：US192166
申请日：1998-11-13
申请人： Ming-I Chen , Yung-Chieh Fan
发明人： Ming-I Chen , Yung-Chieh Fan
IPC分类号： H01L31/112 , H01L21/00
CPC分类号： H01L31/112
摘要： A method for forming a metallic reflecting layer in a semiconductor photodiode including a CMOS photodiode to enhance the sensitivity by filling a trench formed in the isolation next to the depletion region of the semiconductor photodiode with high reflectivity metal. The metal filled in the trench is used as a metallic reflecting layer to increase the number of photons reaching the depletion region by reflecting part of the aslope incident photons. An insulator is formed on the top of the metallic reflecting layer to electrically insulate the metallic reflecting layer from other conducting device formed by the follow-up process.
摘要翻译：一种用于在包括CMOS光电二极管的半导体光电二极管中形成金属反射层的方法，用于通过以高反射率金属填充在隔离层中形成的沟槽，以增强半导体光电二极管的耗尽区域，从而提高灵敏度。填充在沟槽中的金属用作金属反射层，以通过反射部分斜坡入射光子来增加到达耗尽区的光子的数量。在金属反射层的顶部形成绝缘体，以使金属反射层与通过后续处理形成的其它导电装置电绝缘。

4. 发明授权

US6118142A CMOS sensor 失效
标题翻译： CMOS传感器
公开(公告)号：US6118142A
公开(公告)日：2000-09-12
申请号：US189354
申请日：1998-11-09
申请人： Ming-I Chen , Yung-Chieh Fan
发明人： Ming-I Chen , Yung-Chieh Fan
IPC分类号： H01L21/762 , H01L27/146 , H01L27/148 , H01L29/768
CPC分类号： H01L27/14683 , H01L21/76224 , H01L27/14609 , H01L27/1462 , H01L27/1463
摘要： A CMOS sensor structure and method of manufacture that includes the fabrication of a special shallow trench isolation structure. Besides isolating the active region for forming the CMOS sensor device, the shallow trench isolation structure has a special reflective plug embedded inside capable of reflecting incoming light onto the sensitive region of the CMOS sensor. Hence, the interactive length of incoming light with the light sensitive region can be increased, thereby increasing the contrast ratio and light sensitivity of the CMOS sensor.
摘要翻译： CMOS传感器结构和制造方法，其包括制造特殊的浅沟槽隔离结构。除了隔离用于形成CMOS传感器装置的有源区域之外，浅沟槽隔离结构还具有内置的特殊的反射插头，能够将入射光反射到CMOS传感器的敏感区域。因此，可以增加与光敏区域的入射光的交互长度，从而增加CMOS传感器的对比度和光灵敏度。

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