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1. 发明授权

US4958158A Modem with noise-reducing decoder in demodulation of encoded binary pulse signals representative of constant amplitude signals 失效
标题翻译：调制解调器具有降噪解码器解调编码的二进制脉冲信号，代表恒定幅度信号
公开(公告)号：US4958158A
公开(公告)日：1990-09-18
申请号：US184318
申请日：1988-04-21
申请人： Motomu Hashizume , Yukoh Matsumoto
发明人： Motomu Hashizume , Yukoh Matsumoto
IPC分类号： G10L19/00 , H03M3/02
CPC分类号： H03M3/02
摘要： Modem comprising a delta modulation (DM) encoder and a DM decoder which has noise-reducing capability in the demodulation of encoded binary pulse signals representative of constant amplitude signals. The DM decoder includes a 1-click delay circuit operable in conjunction with a logic circuit and an integrator to produce a demodulated output signal which is the same as the preceding signal when the input signals to the DM encoder are constant amplitude signals, thereby eliminating are substantially reducing granular noise arising from a constant analog input to the modem without requiring a special filter. The logic circuit of the DM decoder may be an exclusive NOR gate which compares the 1-clock delayed binary pulse signal with the binary pulse signal and provides a control signal output based upon the comparison. The control signal output from the exclusive NOR gate controls the output of the integrator and enables the integrator to produce a substantially noise-free demodulated output signal.
摘要翻译：调制解调器包括增量调制（DM）编码器和DM解码器，其在解调表示恒定幅度信号的编码二进制脉冲信号中具有降噪能力。 DM解码器包括可与逻辑电路和积分器结合操作的一键延迟电路，以产生与前述信号相同的解调输出信号，当DM编码器的输入信号为恒定振幅信号时，消除大大减少了从调制解调器的恒定模拟输入引起的颗粒噪声，而不需要特殊的滤波器。 DM解码器的逻辑电路可以是异或门，其将1时钟延迟二进制脉冲信号与二进制脉冲信号进行比较，并且基于该比较提供控制信号输出。从异或门输出的控制信号控制积分器的输出，使积分器产生基本无噪声的解调输出信号。

2. 发明申请

US20090024381A1 Simulation device for co-verifying hardware and software 审中-公开
标题翻译：用于共同验证硬件和软件的仿真设备
公开(公告)号：US20090024381A1
公开(公告)日：2009-01-22
申请号：US12155002
申请日：2008-05-28
申请人： Yoshinori Sakamoto , Toshiyuki Tanimizu , Fuyuki Matsubayashi , Ryo Kuya , Tatsuya Yoshino , Hideo Miyake , Masaharu Kimura , Yukoh Matsumoto
发明人： Yoshinori Sakamoto , Toshiyuki Tanimizu , Fuyuki Matsubayashi , Ryo Kuya , Tatsuya Yoshino , Hideo Miyake , Masaharu Kimura , Yukoh Matsumoto
IPC分类号： G06F9/455
CPC分类号： G06F11/3664
摘要： A simulation device capable of verifying coordinated operation of software and hardware faster and more accurately. The simulation device has a framework including a virtual OS and a virtual CPU to execute software under test. The virtual OS and CPU also serve as a first scheduler that manages an execution schedule for the software under test. The framework includes a communication interface for communication between the software under test and hardware models. A second scheduler manages simulation processes of the framework and the hardware model. The virtual OS and CPU release their execution right to the second scheduler according to the execution schedule of the software under test.
摘要翻译：一种能够更快，更准确地验证软件和硬件协调运行的仿真设备。仿真设备具有包括虚拟操作系统和虚拟CPU的框架，用于执行被测软件。虚拟操作系统和CPU也作为第一个调度器来管理被测软件的执行时间表。该框架包括用于在被测软件和硬件模型之间通信的通信接口。第二个调度器管理框架和硬件模型的仿真过程。虚拟操作系统和CPU根据被测软件的执行时间表将其执行权释放到第二个调度程序。

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