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    • 4. 发明授权
    • Transmission circuit and communication system
    • 传输电路和通信系统
    • US08817929B2
    • 2014-08-26
    • US13137261
    • 2011-08-02
    • Yukio Shimomura
    • Yukio Shimomura
    • H04L7/00
    • H04J3/0685H03M9/00H04J3/047
    • A transmission circuit includes: a plurality of lane blocks arranged in parallel to each other configured to convert parallel data supplied from a corresponding lane into serial data and output the serial data; and a clock enabler block including at least one clock enabler for outputting a drive clock phase-locked with a reference clock to the plurality of lane blocks after a plurality of cycles of the drive clock in response to an enable signal. Each of the plurality of lane blocks has a divider for dividing the drive clock supplied from the clock enabler block to generate a divide clock and a load signal, and a parallel-to-serial converter for converting parallel data supplied from the corresponding lane into serial data in synchronization with the divide clock and the load signal generated by the divider and the drive clock generated by the clock enabler block.
    • 传输电路包括:多个并行布置的多个通道块,配置成将从相应通道提供的并行数据转换为串行数据并输出串行数据; 以及时钟使能器块,其包括至少一个时钟使能器,用于响应于使能信号,在所述驱动时钟的多个周期之后,将与参考时钟锁相的驱动时钟输出到所述多个通道块。 多个通道块中的每一个具有用于分割从时钟使能器块提供的驱动时钟以产生除法时钟和负载信号的分频器,以及用于将从相应通道提供的并行数据转换成串行的并行转换器 数据与分频时钟同步,由分频器产生的负载信号和由时钟使能器模块产生的驱动时钟。
    • 5. 发明申请
    • Electricity Generation Device and Permanent-Magnet Electric Generator
    • 发电装置和永磁发电机
    • US20120306462A1
    • 2012-12-06
    • US13485727
    • 2012-05-31
    • Hitoshi OyoriYukio Shimomura
    • Hitoshi OyoriYukio Shimomura
    • G05F1/455
    • H02P9/006H02P9/10H02P29/02
    • An electricity generation device includes a permanent-magnet electric generator with three or more phase windings each having an output terminal and connected to a neutral point, and bidirectional semiconductor switching circuits capable of interrupting connections between the respective phase windings and the neutral point. Each switching circuit allows current to flow in both directions. A gate signal generation circuit outputs to one of the switching circuits during a period including the time at which the AC voltage excited in the corresponding phase winding turns from positive to negative and during a period including the time at which the AC voltage excited in the corresponding phase winding turns from negative to positive. A startup gate signal output circuit outputs a startup gate signal to all of the bidirectional semiconductor switching circuits when the permanent-magnet electric generator is to be started.
    • 发电装置包括具有三个或更多个相绕组的永磁式发电机,每个相绕组具有输出端并连接到中性点,以及能够中断各相绕组和中性点之间的连接的双向半导体开关电路。 每个开关电路允许电流在两个方向上流动。 在包括在相应相绕组中激发的交流电压从正变为负的时间和包括在相应的相位绕组中激发的交流电压的时间的时段期间,门信号产生电路输出到一个开关电路 相绕组从负变为正。 当要启动永久磁铁发电机时,启动门信号输出电路向所有双向半导体开关电路输出启动门信号。
    • 6. 发明申请
    • Transmission circuit and communication system
    • 传输电路和通信系统
    • US20120033748A1
    • 2012-02-09
    • US13137261
    • 2011-08-02
    • Yukio Shimomura
    • Yukio Shimomura
    • H04L27/00
    • H04J3/0685H03M9/00H04J3/047
    • A transmission circuit includes: a plurality of lane blocks arranged in parallel to each other configured to convert parallel data supplied from a corresponding lane into serial data and output the serial data; and a clock enabler block including at least one clock enabler for outputting a drive clock phase-locked with a reference clock to the plurality of lane blocks after a plurality of cycles of the drive clock in response to an enable signal. Each of the plurality of lane blocks has a divider for dividing the drive clock supplied from the clock enabler block to generate a divide clock and a load signal, and a parallel-to-serial converter for converting parallel data supplied from the corresponding lane into serial data in synchronization with the divide clock and the load signal generated by the divider and the drive clock generated by the clock enabler block.
    • 传输电路包括:多个并行布置的多个通道块,配置成将从相应通道提供的并行数据转换为串行数据并输出串行数据; 以及时钟使能器块,其包括至少一个时钟使能器,用于响应于使能信号,在所述驱动时钟的多个周期之后,将与参考时钟锁相的驱动时钟输出到所述多个通道块。 多个通道块中的每一个具有用于分割从时钟使能器块提供的驱动时钟以产生除法时钟和负载信号的分频器,以及用于将从相应通道提供的并行数据转换成串行的并行转换器 数据与分频时钟同步,由分频器产生的负载信号和由时钟使能器模块产生的驱动时钟。