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    • 2. 发明申请
    • ELECTRIC MOTOR APPARATUS
    • 电动马达装置
    • US20100084939A1
    • 2010-04-08
    • US12564490
    • 2009-09-22
    • Hiroto IsodaYuji AkaoYasuki KuwabaraMasahiro FuruyaMasayuki Hada
    • Hiroto IsodaYuji AkaoYasuki KuwabaraMasahiro FuruyaMasayuki Hada
    • H02K21/14
    • H02K37/14H02K1/14H02K1/185
    • An electric motor apparatus providing increased output torque and allowing rotation in a predetermined direction includes a rotor 135 having a permanent magnet having two magnetic poles spaced from each other by approximately 180 degrees about a rotation axis, a stator having a substantially (T-shape (Y-shape) as a whole and having first, second and third magnetic pole portions 112, 114 and 116 disposed around the rotor and connecting portions 122, 124 and 126, which are narrow in their middle regions and each connects between an associated pair of adjacent magnetic pole portions, a first electromagnetic coil 140 inducing a magnetic circuit that passes through the first and second magnetic pole portions, and a second electromagnetic coil 142 inducing a magnetic circuit that passes through the second and third magnetic pole portions. The first and second electromagnetic coils are set parallel to and at opposite sides of the second magnetic pole portion 112. The first electromagnetic coil has one and other ends magnetically coupled to the first and second magnetic pole portions, respectively. The second electromagnetic coil has one and other ends magnetically coupled to the third and second magnetic pole portions, respectively. The first and second electromagnetic coils are selectively excited to control the rotation of the rotor.
    • 提供增加的输出转矩并允许沿预定方向旋转的电动机装置包括转子135,转子135具有永磁体,该永磁体具有相对于旋转轴彼此间隔大约180度的两个磁极,定子具有基本上(T形 Y形),并且具有围绕转子和连接部分122,124和126设置的第一,第二和第三磁极部分112,114和116,所述第一,第二和第三磁极部分112,114和116在其中间区域中窄,并且各自连接在相关联的一对 相邻的磁极部分,引导通过第一和第二磁极部分的磁路的第一电磁线圈140和引起通过第二和第三磁极部分的磁路的第二电磁线圈142,第一和第二磁极 电磁线圈平行于第二磁极部分112的相对侧设置 l具有分别磁耦合到第一和第二磁极部分的一个和另一个端部。 第二电磁线圈分别具有磁耦合到第三和第二磁极部分的一端和另一端。 选择性地激励第一和第二电磁线圈以控制转子的旋转。
    • 5. 发明申请
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US20050236368A1
    • 2005-10-27
    • US11103375
    • 2005-04-11
    • Yuji Akao
    • Yuji Akao
    • B24B53/00B24B1/00B24B37/04B24B53/017B44C1/22H01L21/302H01L21/304H01L21/306H01L21/3105H01L21/3205H01L21/321H01L21/768
    • H01L21/31053B24B37/042H01L21/02052
    • A method for manufacturing a semiconductor device comprises the steps of: giving chemical mechanical polishing to a polishee layer, provided on a semiconductor substrate, by contacting a conditioner against the surface of a polishing pad while contacting the semiconductor substrate, having the polishee layer, against the surface of the polishing pad; cleaning the polishing pad, after giving chemical mechanical polishing to the polishee layer, by supplying a cleaning liquid onto the polishing pad while contacting the conditioner against the polishing pad; cleaning the surface of the semiconductor substrate by contacting the semiconductor substrate 1 against the cleaned polishing pad while supplying the cleaning liquid onto the polishing pad; and giving finish-cleaning to the surface of the semiconductor substrate by contacting the semiconductor substrate against the cleaned polishing pad while supplying the cleaning liquid onto the polishing pad.
    • 一种制造半导体器件的方法包括以下步骤:通过使调理剂与抛光垫的表面接触,同时使具有所述抛光层的半导体衬底接触调节器,抵抗 抛光垫的表面; 通过在将调节器与抛光垫接触的同时向抛光垫上提供清洁液体,在对抛光垫进行化学机械抛光之后,清洁抛光垫; 通过使半导体衬底1与清洁的抛光垫接触,同时将清洁液体供应到抛光垫上来清洁半导体衬底的表面; 并且通过使半导体衬底抵靠清洁过的抛光垫,同时将清洁液体供应到抛光垫上,从而对半导体衬底的表面进行清洁。
    • 6. 发明授权
    • Skin material for interior material
    • 内部材料的外观材料
    • US08448475B2
    • 2013-05-28
    • US13081285
    • 2011-04-06
    • Yuji AkaoFumio Shirasaki
    • Yuji AkaoFumio Shirasaki
    • D04B9/06
    • D04B21/16D10B2403/0112D10B2505/08
    • The skin material for an interior material, formed of a three-dimensional warp knitted fabric includes: front and back ground parts, each of which is formed with knitting yarns guided by at least two guide bars and has at least two knitting patterns, and connecting yarns that connect the front and back ground parts, wherein: the front ground part has a cord stitch pattern and another knitting pattern; a sum of a number of loops of the cord stitch pattern and a number of loops of the another knitting pattern is smaller than a sum of numbers of loops of the at least two knitting pattern forming the back ground part; and a ratio of the number of loops of the another knitting pattern with respect to the number of loops of the cord stitch pattern is from 20 to 80%.
    • 由三维经编织物形成的用于内部材料的表层材料包括:前后接地部分,每个织物由至少两个导杆引导的编织纱线形成,并且具有至少两个编织图案,并且连接 连接前后接地部的纱线,其特征在于:前地面部具有绳针迹图案和另一编织图案; 帘线针迹图案的多个圈数和另一编织图案的多个圈数的和小于形成背部接地部分的至少两个编织图案的圈数之和; 并且另一编织图案的线圈数相对于帘线针迹图案的圈数的比率为20〜80%。
    • 7. 发明授权
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US07897466B2
    • 2011-03-01
    • US12142011
    • 2008-06-19
    • Yuji Akao
    • Yuji Akao
    • H01L21/00
    • H01L21/823462H01L21/76816H01L21/823437H01L21/823475H01L23/585H01L2924/0002H01L2924/00
    • There is provided a method for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor provided on a same semiconductor substrate. The method includes forming a first gate electrode of the high breakdown voltage transistor and a second gate electrode of the low breakdown voltage transistor on a transistor formation area of the substrate, as well as a dummy gate electrode on a dummy pattern formation area of the substrate; forming an interlayer insulation film on the substrate so as to cover the first and the second gate electrodes and the dummy gate electrode; and forming a first contact hole on the first gate electrode, a second contact hole on the second gate electrode, and a dummy contact hole on the dummy gate electrode, respectively, by partially dry etching the interlayer insulation film, wherein in the formation of the contact holes, a top surface of the dummy gate electrode is exposed at a bottom of the dummy contact hole before a top surface of the first gate electrode is exposed at a bottom of the first contact hole.
    • 提供一种用于制造具有高击穿电压晶体管和设置在同一半导体衬底上的低击穿电压晶体管的半导体器件的方法。 该方法包括在衬底的晶体管形成区域上形成高击穿电压晶体管的第一栅电极和低击穿电压晶体管的第二栅电极,以及在衬底的虚设图形形成区域上的虚拟栅极电极 ; 在所述基板上形成层间绝缘膜,以覆盖所述第一和第二栅电极和所述伪栅电极; 以及分别在所述第一栅电极上形成第一接触孔,在所述第二栅电极上形成第二接触孔,以及在所述伪栅电极上形成虚拟接触孔,通过部分干蚀刻所述层间绝缘膜, 在第一接触孔的底部露出第一栅电极的顶表面之前,在虚拟接触孔的底部暴露虚拟栅电极的顶表面。
    • 8. 发明申请
    • Method for Manufacturing Semiconductor Device
    • 半导体器件制造方法
    • US20080318393A1
    • 2008-12-25
    • US12142011
    • 2008-06-19
    • Yuji AKAO
    • Yuji AKAO
    • H01L21/8234
    • H01L21/823462H01L21/76816H01L21/823437H01L21/823475H01L23/585H01L2924/0002H01L2924/00
    • There is provided a method for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor provided on a same semiconductor substrate. The method includes forming a first gate electrode of the high breakdown voltage transistor and a second gate electrode of the low breakdown voltage transistor on a transistor formation area of the substrate, as well as a dummy gate electrode on a dummy pattern formation area of the substrate; forming an interlayer insulation film on the substrate so as to cover the first and the second gate electrodes and the dummy gate electrode; and forming a first contact hole on the first gate electrode, a second contact hole on the second gate electrode, and a dummy contact hole on the dummy gate electrode, respectively, by partially dry etching the interlayer insulation film, wherein in the formation of the contact holes, a top surface of the dummy gate electrode is exposed at a bottom of the dummy contact hole before a top surface of the first gate electrode is exposed at a bottom of the first contact hole.
    • 提供一种用于制造具有高击穿电压晶体管和设置在同一半导体衬底上的低击穿电压晶体管的半导体器件的方法。 该方法包括在衬底的晶体管形成区域上形成高击穿电压晶体管的第一栅电极和低击穿电压晶体管的第二栅电极,以及在衬底的虚设图形形成区域上的虚拟栅极电极 ; 在所述基板上形成层间绝缘膜,以覆盖所述第一和第二栅电极和所述伪栅电极; 以及分别在所述第一栅电极上形成第一接触孔,在所述第二栅电极上形成第二接触孔,以及在所述伪栅电极上形成虚拟接触孔,通过部分干蚀刻所述层间绝缘膜, 在第一接触孔的底部露出第一栅电极的顶表面之前,在虚拟接触孔的底部暴露虚拟栅电极的顶表面。
    • 10. 发明申请
    • SKIN MATERIAL FOR INTERIOR MATERIAL
    • 用于内部材料的皮肤材料
    • US20110247370A1
    • 2011-10-13
    • US13081285
    • 2011-04-06
    • Yuji AKAOFumio Shirasaki
    • Yuji AKAOFumio Shirasaki
    • D04B21/00
    • D04B21/16D10B2403/0112D10B2505/08
    • The skin material for an interior material, formed of a three-dimensional warp knitted fabric includes: front and back ground parts, each of which is formed with knitting yarns guided by at least two guide bars and has at least two knitting patterns, and connecting yarns that connect the front and back ground parts, wherein: the front ground part has a cord stitch pattern and another knitting pattern; a sum of a number of loops of the cord stitch pattern and a number of loops of the another knitting pattern is smaller than a sum of numbers of loops of the at least two knitting pattern forming the back ground part; and a ratio of the number of loops of the another knitting pattern with respect to the number of loops of the cord stitch pattern is from 20 to 80%.
    • 由三维经编织物形成的用于内部材料的表层材料包括:前后接地部分,每个织物由至少两个导杆引导的编织纱线形成,并且具有至少两个编织图案,并且连接 连接前后接地部的纱线,其特征在于:前地面部具有绳针迹图案和另一编织图案; 帘线针迹图案的多个圈数与另一编织图案的多个圈数的和小于形成背部接地部分的至少两个编织图案的圈数之和; 并且另一编织图案的线圈数相对于帘线针迹图案的圈数的比率为20〜80%。