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1. 发明申请

US20120175745A1 METHODS FOR FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES USING THE SAME 审中-公开
标题翻译：使用其制造半导体器件和半导体器件的方法
公开(公告)号：US20120175745A1
公开(公告)日：2012-07-12
申请号：US12986147
申请日：2011-01-06
申请人： Pin Yuan Su , Weitung Yang , Yu-Chung Fang
发明人： Pin Yuan Su , Weitung Yang , Yu-Chung Fang
IPC分类号： H01L29/06 , H01L21/306 , H01L21/308
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76229
摘要： A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.
摘要翻译：提供了制造半导体器件的精细图案的方法。该方法包括在衬底上形成基底层，具有第一宽度具有相同特征的第一掩模图案和具有相反特征的第二宽度的第二掩模图案，其中在任何两个相邻的倾斜侧壁之间的最小距离等于第二个宽度。通过使用第一掩模图案作为蚀刻掩模来蚀刻基底层以形成第二宽度的第一开口，并且覆盖基底形成填充层。去除第二掩模图案以在填充层中形成第二开口，然后通过第二开口蚀刻第一掩模图案和基底层以形成第三开口。去除填充层和第一掩模图案以形成具有相同特征的第三宽度的基底层的图案，其中基底层图案的特征的第三宽度等于第二宽度。

2. 发明授权

US07713855B2 Method for forming bit-line contact plug and transistor structure 有权
标题翻译：用于形成位线接触插头和晶体管结构的方法
公开(公告)号：US07713855B2
公开(公告)日：2010-05-11
申请号：US11780484
申请日：2007-07-20
申请人： Yu-Chung Fang , Hong-Wen Lee , Kuo-Chung Chen , Jen-Jui Huang , Jing-Kae Liou
发明人： Yu-Chung Fang , Hong-Wen Lee , Kuo-Chung Chen , Jen-Jui Huang , Jing-Kae Liou
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76834 , H01L21/76885 , H01L21/76895 , H01L27/10888
摘要： A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.
摘要翻译：一种用于形成位线接触插塞的方法包括：提供包括晶体管的衬底，所述晶体管在栅极结构的两侧包括栅极结构和源极/漏极; 形成导电层，位线接触材料层和硬掩模层; 执行使用导电层作为蚀刻停止层的蚀刻工艺，以蚀刻位线接触材料层和硬掩模层，并在源极/漏极上形成位线接触插塞。晶体管结构包括在栅极结构的两侧处的栅极结构和源极/漏极，覆盖栅极结构的一部分并连接到源极/漏极的导电层，以及布置在导电层上的位线接触插塞，直接连接到导电层。

3. 发明申请

US20080268640A1 METHOD FOR FORMING BIT-LINE CONTACT PLUG AND TRANSISTOR STRUCTURE 有权
标题翻译：用于形成位线接触插入和晶体管结构的方法
公开(公告)号：US20080268640A1
公开(公告)日：2008-10-30
申请号：US11780484
申请日：2007-07-20
申请人： Yu-Chung Fang , Hong-Wen Lee , Kuo-Chung Chen , Jen-Jui Huang , Jing-Kae Liou
发明人： Yu-Chung Fang , Hong-Wen Lee , Kuo-Chung Chen , Jen-Jui Huang , Jing-Kae Liou
IPC分类号： H01L21/441 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76834 , H01L21/76885 , H01L21/76895 , H01L27/10888
摘要： A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.
摘要翻译：一种用于形成位线接触插塞的方法包括：提供包括晶体管的衬底，所述晶体管在栅极结构的两侧包括栅极结构和源极/漏极; 形成导电层，位线接触材料层和硬掩模层; 执行使用导电层作为蚀刻停止层的蚀刻工艺，以蚀刻位线接触材料层和硬掩模层，并在源极/漏极上形成位线接触插塞。晶体管结构包括在栅极结构的两侧处的栅极结构和源极/漏极，覆盖栅极结构的一部分并连接到源极/漏极的导电层，以及布置在导电层上的位线接触插塞，直接连接到导电层。

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