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1. 发明授权

US6138133A Circuit for calculating the inverse of an arbitrary element of a finite field 失效
标题翻译：用于计算有限域的任意元素的逆的电路
公开(公告)号：US6138133A
公开(公告)日：2000-10-24
申请号：US99275
申请日：1998-06-18
申请人： Young-Uk Oh
发明人： Young-Uk Oh
IPC分类号： G06F11/10 , G06F7/496 , G06F7/52 , G06F7/72 , H03M7/30 , H03M13/00 , G06F7/00
CPC分类号： G06F7/726
摘要： A combinational logic type inversion circuit for calculating the inverse of an arbitrary element .alpha..sup.i in a finite field, includes a power and multiplication circuit for calculating a primitive element .alpha..sup.i raised to the (2.sup.1)-th power through a primitive element .alpha..sup.i raised to the (2.sup.m-1)-th power and multiplying all of the primitive elements .alpha..sup.i raised to the (2.sup.1)-th power through .alpha..sup.i raised to the (2.sup.m-1)-th power together to generate an output M.sub.OUT, and a divider circuit for dividing the output M.sub.OUT of the power and multiplication circuit by the primitive element .alpha. raised to the (2.sup.m -1)-th power.
摘要翻译：用于计算有限域中的任意元素αi的逆的组合逻辑类型反转电路包括功率和乘法电路，用于通过提供的原始元素αi来计算提高到第（21）个功率的原始元素αi （2m-1）的功率，并且通过αi将所有提高到（21）功率的所有原始元素乘以（i）提高到（2m-1）功率，以产生输出MOUT，以及用于将功率和乘法电路的输出MOUT除以由（2m-1）功率提升的原始元素α的分频器电路。

2. 发明授权

US5805616A Circuit of calculating errata locator and evaluator polynomial, calculating method thereof and reed-solomon decoder using the same 失效
标题翻译：计算勘误定位器和求值多项式的电路，其计算方法和使用其的簧片独奏解码器
公开(公告)号：US5805616A
公开(公告)日：1998-09-08
申请号：US552551
申请日：1996-03-20
申请人： Young-uk Oh
发明人： Young-uk Oh
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/151
摘要： The present invention relates to a circuit for calculating an ELP and an EEP, and a Reed-Solomon decoder using the same. The circuit includes: first storage device for storing a syndrome value, coefficient values of the ELP, a discrepancy value and the size of a shortened code; second storage device for storing the coefficient values of the ELP, the reciprocal value of the discrepancy, the discrepancy value, the coefficient values of the ELP and the values obtained by differentiating the coefficient values of the ELP; first selecting device for selectively outputting the values stored in the first storage device in response to first to sixth control signals; second selecting device for selectively outputting the values stored in the second storage device in response to the control signals; multiplication device for multiplying the values selected by the first and second selecting means; third selecting means for selectively outputting the resultant values multiplied by the multiplication device in response to the control signals; third storage device for storing the resultant values selectively output by said third selecting device. Accordingly, the construction of the circuit becomes simple and a chip area can be reduced at the time of integration.
摘要翻译：本发明涉及一种用于计算ELP和EEP的电路，以及使用该电路的Reed-Solomon解码器。该电路包括：用于存储校正子值的第一存储装置，ELP的系数值，差值和缩短代码的大小; 用于存储ELP的系数值，差异的倒数值，偏差值，ELP的系数值和通过微分ELP的系数值而获得的值的第二存储装置; 第一选择装置，用于响应于第一至第六控制信号选择性地输出存储在第一存储装置中的值; 第二选择装置，用于响应于控制信号选择性地输出存储在第二存储装置中的值; 乘法装置，用于将由第一和第二选择装置选择的值相乘; 第三选择装置，用于响应于控制信号选择性地输出乘以乘法装置的结果值; 第三存储装置，用于存储由所述第三选择装置有选择地输出的结果值。因此，电路的结构变得简单，并且在集成时可以减小芯片面积。

3. 发明授权

US5583499A Method and apparatus for computing error locator polynomial for use in a Reed-Solomon decoder 失效
标题翻译：用于计算用于Reed-Solomon解码器的误差定位多项式的方法和装置
公开(公告)号：US5583499A
公开(公告)日：1996-12-10
申请号：US365256
申请日：1994-12-28
申请人： Young-Uk Oh , Dae-Young Kim
发明人： Young-Uk Oh , Dae-Young Kim
IPC分类号： G06F11/10 , H03M13/00 , H03M13/15
CPC分类号： H03M13/151
摘要： In a decoding system which decodes a transmitted signal encoded by using a Reed-Solomon code, an error locator polynomial of the nth iteration is calculated based on a predetermined number of syndrome values; a group of variables of the (n-1)st iteration including a discrepancy and an error locator polynomial thereof; and an error locator polynomial of the (n-2)nd iteration. The method for providing the error locator polynomial comprises the steps of calculating a discrepancy of the nth iteration based on the syndrome values and the error locator polynomial of the (n-1)st iteration; calculating a temporal term based on the discrepancy of the (n-1)st iteration and the error locator polynomial of the (n-2)nd iteration; determining a correction term based on the temporal term and the discrepancy of the nth iteration; and computing the error locator polynomial of the nth iteration based on the correction term and the error locator polynomial of the (n-1)st iteration.
摘要翻译：在对利用Reed-Solomon码编码的发送信号进行解码的解码系统中，基于预定数量的校正子值计算第n次迭代的误差定位多项式; （n-1）次迭代的一组变量包括差异和其错误定位多项式; 和（n-2）nd迭代的误差定位多项式。提供错误定位多项式的方法包括基于第（n-1）次迭代的校正子值和误差定位多项式计算第n次迭代的差异的步骤; 基于第（n-1）次迭代和第（n-2）次迭代的误差定位多项式的差异来计算时间项; 基于第n次迭代的时间项和差异确定校正项; 以及基于第（n-1）次迭代的校正项和误差定位多项式来计算第n次迭代的误差定位多项式。

4. 发明授权

US5712880A Traceback-performing apparatus in viterbi decoder 失效
标题翻译：维特比解码器中的追溯执行装置
公开(公告)号：US5712880A
公开(公告)日：1998-01-27
申请号：US557539
申请日：1995-11-14
申请人： Min-joong Rim , Young-uk Oh
发明人： Min-joong Rim , Young-uk Oh
IPC分类号： H04N19/00 , G11B20/18 , H03M13/23 , H03M13/41 , H04N19/42 , H04N19/423 , H04N19/65 , H04N21/438 , H03D1/00
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/41 , H03M13/4169 , H03M13/6505
摘要： A traceback-performing apparatus includes a first storing portion which receives and stores new path metric values and minimum path metric value so that the first input value is output later and the later input value is output first. A first trace logic portion which receives outputs of the first storing portion and the minimum path metric value and generates a first state which is the next state to be traced. A second storing portion which receives and stores the output of the first storing portion so that the first input value is output first and the later input value is output later. A second trace logic portion which receives the output of the second storing portion and the first state and generates a second state which is the next state to be traced. And, a third storing portion which receives and stores the second state so that the first input value is output later and the later input value is output first so as to find the decoded bits. Therefore, cost is saved in embodying the Viterbi decoder in a VLSI by reducing the required chip area, simplifying address-generation and eliminating the need for global interconnection.
摘要翻译：回溯执行装置包括第一存储部分，其接收并存储新的路径量度值和最小路径度量值，使得第一输入值稍后输出，并且稍后输入的值被首先输出。第一跟踪逻辑部分，其接收第一存储部分的输出和最小路径量度值，并产生作为要跟踪的下一状态的第一状态。第二存储部分，其接收并存储第一存储部分的输出，使得第一输入值首先被输出，后来的输入值稍后输出。第二跟踪逻辑部分，其接收第二存储部分的输出和第一状态，并产生作为要跟踪的下一个状态的第二状态。以及第三存储部分，其接收并存储第二状态，使得第一输入值稍后输出，并且先输出稍后的输入值以便找到解码的位。因此，通过减少所需的芯片面积，简化地址生成并消除对全局互连的需要，可以节省在VLSI中体现维特比解码器的成本。

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