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1. 外观设计

USD459706S1 Hybrid integrated circuit device 失效
公开(公告)号：USD459706S1
公开(公告)日：2002-07-02
申请号：US29145538
申请日：2001-07-26
申请人： Hitoshi Ebihara , Naoki Tomaru , Yoshiyuki Wasada , Tetsuya Ito , Hideki Kato , Tomohiro Igarashi , Hideki Yoda
设计人： Hitoshi Ebihara , Naoki Tomaru , Yoshiyuki Wasada , Tetsuya Ito , Hideki Kato , Tomohiro Igarashi , Hideki Yoda

2. 外观设计

USD466093S1 Hybird integrated circuit board 失效
标题翻译： Hybird集成电路板
公开(公告)号：USD466093S1
公开(公告)日：2002-11-26
申请号：US29145536
申请日：2001-07-26
申请人： Hitoshi Ebihara , Naoki Tomaru , Yoshiyuki Wasada , Tetsuya Ito , Hideki Kato , Tomohiro Igarashi , Hideki Yoda
设计人： Hitoshi Ebihara , Naoki Tomaru , Yoshiyuki Wasada , Tetsuya Ito , Hideki Kato , Tomohiro Igarashi , Hideki Yoda

3. 发明授权

US06353309B1 Switching circuit having a switching semiconductor device and control method thereof 失效
标题翻译：具有开关半导体器件的开关电路及其控制方法
公开(公告)号：US06353309B1
公开(公告)日：2002-03-05
申请号：US09608023
申请日：2000-06-29
申请人： Mitsuaki Ootani , Yoshiyuki Wasada , Nobuyuki Yamazaki , Yasushi Inoue , Takeshi Nakayama , Junichi Shimamura , Yuji Ebinuma , Takayuki Tsukamoto
发明人： Mitsuaki Ootani , Yoshiyuki Wasada , Nobuyuki Yamazaki , Yasushi Inoue , Takeshi Nakayama , Junichi Shimamura , Yuji Ebinuma , Takayuki Tsukamoto
IPC分类号： G05F140
CPC分类号： G05F1/575 , H03K17/122
摘要： The present invention provides a switching circuit and an electronic switching component having a switching semiconductor device to perform switching between a conducting state and a non-conducting state of a conducting path to thereby reduce the power loss thereof and a control method thereof. In the present invention, at least two FETs 11 and 12, wherein the FET 11 has a faster switching time and the FET 12 has a lower ON resistance. Active terminals (drains and sources) of the FETs 11 and 12 are connected to each other in parallel. By employing these FETs 11 and 12, the conversion between an ON-state and an OFF-state of the conducting path is performed. In converting from the non-conducting state to the conducting state, the control circuit 13 first turns on the FET 11 and then turns on the FET 12 when if a voltage between terminals of the FET 11 reaches around a saturation value thereof. In converting from the conducting state to the non-conducting state, the control circuit 13 first turns off the FET 12 and then turns off the FET 11 when if a voltage between terminals of the FET 11 reaches around a saturation value thereof.
摘要翻译：本发明提供一种开关电路和具有开关半导体器件的电子开关元件，以进行导通路径的导通状态和非导通状态之间的切换，从而降低其功率损耗及其控制方法。在本发明中，至少两个FET 11和12，其中FET 11具有更快的开关时间，并且FET 12具有较低的导通电阻。 FET 11和12的有源端子（漏极和源极）并联连接。通过采用这些FET11,12，进行导通路径的导通状态和截止状态之间的转换。在从非导通状态转换为导通状态时，如果FET 11的端子之间的电压达到其饱和值，则控制电路13首先接通FET 11，然后导通FET 12。在从导通状态转换为非导通状态时，如果FET 11的端子之间的电压达到其饱和值，则控制电路13首先关断FET 12，然后关断FET 11。

4. 外观设计

USD471167S1 Hybrid integrated circuit board 失效
标题翻译：混合集成电路板
公开(公告)号：USD471167S1
公开(公告)日：2003-03-04
申请号：US29158467
申请日：2002-04-05
申请人： Hitoshi Ebihara , Naoki Tomaru , Yoshiyuki Wasada , Tetsuya Ito , Hideki Kato , Tomohiro Igarashi , Hideki Yoda
设计人： Hitoshi Ebihara , Naoki Tomaru , Yoshiyuki Wasada , Tetsuya Ito , Hideki Kato , Tomohiro Igarashi , Hideki Yoda

5. 外观设计

USD465463S1 Hybrid integrated circuit device 失效
公开(公告)号：USD465463S1
公开(公告)日：2002-11-12
申请号：US29155761
申请日：2002-02-19
申请人： Yoshiyuki Wasada , Tetsuya Ito , Naoki Tomaru
设计人： Yoshiyuki Wasada , Tetsuya Ito , Naoki Tomaru

6. 外观设计

USD456787S1 Hybrid integrated circuit device 失效
标题翻译：混合集成电路器件
公开(公告)号：USD456787S1
公开(公告)日：2002-05-07
申请号：US29143470
申请日：2001-06-15
申请人： Yoshiyuki Wasada , Tetsuya Ito , Naoki Tomaru
设计人： Yoshiyuki Wasada , Tetsuya Ito , Naoki Tomaru

7. 发明授权

US06232562B1 Hybrid integrated circuit device 失效
标题翻译：混合集成电路器件
公开(公告)号：US06232562B1
公开(公告)日：2001-05-15
申请号：US09406717
申请日：1999-09-28
申请人： Kiichi Kikuchi , Yuji Ebinuma , Yasuo Hosaka , Yoshiyuki Wasada , Kenji Kaneta , Hajime Hasegawa , Mitsuaki Ootani
发明人： Kiichi Kikuchi , Yuji Ebinuma , Yasuo Hosaka , Yoshiyuki Wasada , Kenji Kaneta , Hajime Hasegawa , Mitsuaki Ootani
IPC分类号： H05K116
CPC分类号： H05K1/0218 , H05K1/181 , H05K2201/0715 , H05K2201/0792 , H05K2201/093 , H05K2201/09336 , H05K2201/1003 , Y02P70/611
摘要： A hybrid integrated circuit device is provided which suppresses lowering of the inductance value of a mounted coil component. A hybrid integrated circuit device according to the present invention has such a structure that a wiring pattern is provided on at least one main face of a substrate, a laid core type coil component is mounted on at least one main surface of the substrate, and a conductor pattern including a ground pattern is provided at least either on a main face opposite to the surface of the substrate upon which the laid core type coil component is mounted or in an interior of the substrate. In particular, the hybrid integrated circuit device has a configuration such that a magnetic flux passing window, having an absence of ground pattern, is provided in an orthographic projection area corresponding to a winding portion of the coil component in the conductor pattern.
摘要翻译：提供一种混合集成电路器件，其抑制安装的线圈部件的电感值的降低。根据本发明的混合集成电路器件具有在基板的至少一个主面上设置布线图案的结构，在基板的至少一个主表面上安装铺设的芯型线圈部件，在与放置的芯型线圈部件的基板的表面相反的主面上或者在基板的内部，至少提供包括接地图案的导体图案。特别地，混合集成电路器件具有这样的结构，即在与导体图案中的线圈部件的绕组部分对应的正投影区域中设置不具有接地图案的磁通通过窗口。

8. 外观设计

USD471524S1 Hybrid integrated circuit device 失效
公开(公告)号：USD471524S1
公开(公告)日：2003-03-11
申请号：US29158473
申请日：2002-04-05
申请人： Hitoshi Ebihara , Naoki Tomaru , Yoshiyuki Wasada , Tetsuya Ito , Hideki Kato , Tomohiro Igarashi , Hideki Yoda
设计人： Hitoshi Ebihara , Naoki Tomaru , Yoshiyuki Wasada , Tetsuya Ito , Hideki Kato , Tomohiro Igarashi , Hideki Yoda

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