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1. 发明授权

US06226270B1 Method and apparatus for path trace check 失效
标题翻译：路径跟踪检查的方法和装置
公开(公告)号：US06226270B1
公开(公告)日：2001-05-01
申请号：US09122412
申请日：1998-07-24
申请人： Isao Chiku , Toru Kosugi , Yoshihiro Yatagai , Yoshitaka Taki
发明人： Isao Chiku , Toru Kosugi , Yoshihiro Yatagai , Yoshitaka Taki
IPC分类号： H04L1257
CPC分类号： H04L43/50 , H04J3/0685 , H04J3/14 , H04J2203/0042 , H04J2203/0057
摘要： A method for a path trace check reducing a load on a computer, raising the speed of the check, and easily enabling an increase of nodes to be added. On a sender side, a first computer simply generates path trace data, adds a specific code CR to this, multiplexes this to the transmission data, then transmits the same to a transmission line. On a receiver side, a second computer simply generates an expected value of the path trace data, autonomously compares this expected value and the actual path trace data extracted from the received transmission data by using the specific code, and determines coincidence of the two.
摘要翻译：用于路径跟踪检查的方法减少计算机上的负载，提高检查速度，并且容易地增加要添加的节点。在发送方，第一台计算机简单地生成路径跟踪数据，向其中添加特定代码CR，将其复用到发送数据，然后将其发送到传输线。在接收机侧，第二计算机简单地生成路径轨迹数据的预期值，通过使用特定的代码自主地比较该期望值和从接收的发送数据提取的实际路径跟踪数据，并且确定两者的一致性。

2. 发明授权

US5955959A Synchronization message transmitting apparatus 失效
标题翻译：同步消息发送装置
公开(公告)号：US5955959A
公开(公告)日：1999-09-21
申请号：US783066
申请日：1997-01-15
申请人： Yoshitaka Taki , Kazuhiko Hata , Junji Yamamoto
发明人： Yoshitaka Taki , Kazuhiko Hata , Junji Yamamoto
IPC分类号： H04L1/20 , H04J3/00 , H04J3/06 , H04J3/14 , H04J3/16 , H04L7/00 , H04M3/22
CPC分类号： H04J3/1611 , H04J3/0685
摘要： A synchronization message transmitting apparatus employs a synchronization message to synchronize a communication network. If an abnormality occurs in any part of the apparatus or on a clock in the apparatus, the apparatus detects the abnormality and prepares a synchronization message indicating that a frame to be transmitted must not be used for preparing a master clock. An opposite party that receives the frame with the synchronization message will not use the received frame for preparing a master clock.
摘要翻译：同步消息发送装置采用同步消息来同步通信网络。如果设备的任何部分或装置的时钟发生异常，则装置检测异常，并准备指示要发送的帧不能用于准备主时钟的同步消息。用同步消息接收帧的对方不会使用接收到的帧来准备主时钟。

3. 发明授权

US07830808B2 Path status monitoring method and device 有权
标题翻译：路径状态监控方法和设备
公开(公告)号：US07830808B2
公开(公告)日：2010-11-09
申请号：US12005608
申请日：2007-12-28
申请人： Osamu Takeuchi , Yoshitaka Taki , Satoru Saitoh , Hiroyuki Honma , Tomoyoshi Fujimori
发明人： Osamu Takeuchi , Yoshitaka Taki , Satoru Saitoh , Hiroyuki Honma , Tomoyoshi Fujimori
IPC分类号： G01R31/08
CPC分类号： H04J3/085
摘要： In a path status monitoring method and device which can enhance or reduce a band more rapidly, for example, SONET frames FR serially connected over 32 frames to which frame Nos. FN (“0”-“31”)) are assigned are cyclically generated respectively for paths P0-P2 in a cycle TC (=64 ms). After output timing delays TD0-TD2 of the frames FR are shifted by an optimal delay interval D (=21 ms) between the paths P0-P2 based on the number of the paths “3”, the output timing delays TD1 and TD2 are restored by preliminarily obtained transmission delays for the paths P1 and P2 to the path P0. When the frames FR are transmitted through each of the paths P0-P2, statuses (path statuses MST) where a reception fault has occurred in each of the paths P0-P2 are collected to be stored in the frame whose frame No. FN=“0”.
摘要翻译：在可以更快速地增强或减少频带的路径状态监视方法和装置中，例如，循环地生成分配了帧号FN（“0”〜“31”）的32帧的串行连接的SONET帧FR 分别用于循环TC（= 64ms）中的路径P0-P2。在帧FR的输出定时延迟TD0-TD2之后，基于路径“3”的数量，在路径P0-P2之间移动最佳延迟间隔D（= 21ms），恢复输出定时延迟TD1和TD2 通过预先获得路径P1和P2到路径P0的传输延迟。当通过路径P0-P2中的每一个发送帧FR时，收集在每个路径P0-P2中发生接收故障的状态（路径状态MST）以存储在帧号FN =“ 0“。

4. 发明申请

US20080159156A1 Path status monitoring method and device 有权
标题翻译：路径状态监控方法和设备
公开(公告)号：US20080159156A1
公开(公告)日：2008-07-03
申请号：US12005608
申请日：2007-12-28
申请人： Osamu Takeuchi , Yoshitaka Taki , Satoru Saitoh , Hiroyuki Honma , Tomoyoshi Fujimori
发明人： Osamu Takeuchi , Yoshitaka Taki , Satoru Saitoh , Hiroyuki Honma , Tomoyoshi Fujimori
IPC分类号： G06F11/00
CPC分类号： H04J3/085
摘要： In a path status monitoring method and device which can enhance or reduce a band more rapidly, for example, SONET frames FR serially connected over 32 frames to which frame Nos. FN (“0”-“31”)) are assigned are cyclically generated respectively for paths P0-P2 in a cycle TC (=64 ms). After output timing delays TD0-TD2 of the frames FR are shifted by an optimal delay interval D (=21 ms) between the paths P0-P2 based on the number of the paths “3”, the output timing delays TD1 and TD2 are restored by preliminarily obtained transmission delays for the paths P1 and P2 to the path P0. When the frames FR are transmitted through each of the paths P0-P2, statuses (path statuses MST) where a reception fault has occurred in each of the paths P0-P2 are collected to be stored in the frame whose frame No. FN=“0”.
摘要翻译：在可以更快速地增强或减少频带的路径状态监视方法和装置中，例如，循环地生成分配了帧号FN（“0”〜“31”）的32帧的串行连接的SONET帧FR 分别用于循环T C C（= 64ms）中的路径P 0 -P 2。在帧FR的输出定时延迟之后，在路径P 0 -P 2之间移动最佳延迟间隔D（= 21ms）基于路径“3”的数量，通过预先获得的路径P 1和P的传输延迟来恢复输出定时延迟T 1 D 2和T 2 D 当通过路径P 0 -P 2中的每一个发送帧FR时，将各路径P 0 -P 2中发生接收故障的状态（路径状态MST）收集为存储在帧号FN =“0”的帧中。

5. 发明授权

US5706280A Transmission quality monitoring system for a digital communication network 失效
标题翻译：数字通信网传输质量监控系统
公开(公告)号：US5706280A
公开(公告)日：1998-01-06
申请号：US507876
申请日：1995-07-27
申请人： Toru Kosugi , Yoshitaka Taki
发明人： Toru Kosugi , Yoshitaka Taki
IPC分类号： H04J1/16 , H04J3/00 , H04J3/14 , H04L12/26 , H04L29/14 , H04M3/24
CPC分类号： H04L43/00 , H04J3/14 , H04L12/26 , H04M3/244
摘要： A digital communication network has a first end office which includes a first multiplexer unit and a second end office which includes a second multiplexer unit. The network performs transmission and reception of multiplexed signals between the first end office and the second end office. A monitor unit is provided within the first end office. Monitoring is performed of the accuracy of the signal received by the second end office from the first end office, signal accuracy information with regard to the received signal being included as subsignalling information in the input signal Sin which is input to the first end office from the second end office. The subsignalling information is extracted by the monitor unit from the input signal, so as to enable monitoring of the signal accuracy of the input signal. The result is a significant improvement in the improvement of transmission quality monitoring service provided in the digital communication network.
摘要翻译：数字通信网络具有包括第一多路复用器单元和包括第二多路复用器单元的第二端部的第一端部。网络在第一端部和第二端部之间进行复用信号的发送和接收。在第一个办公室内提供一个监视器单元。执行第二端部从第一端部接收到的信号的精度的监视，将接收到的信号的信号精度信息作为从第一端部输入的输入信号Sin中的信号信号Sin输入到第一端部第二局监控单元从输入信号提取子信息，以便监视输入信号的信号精度。结果是在数字通信网络中提供的传输质量监测服务的改进方面取得了显着的进步。

6. 发明授权

US06222892B1 Synchronization message reception processing apparatus 失效
标题翻译：同步消息接收处理装置
公开(公告)号：US06222892B1
公开(公告)日：2001-04-24
申请号：US08828891
申请日：1997-03-31
申请人： Yoshitaka Taki , Kazuhiko Hata , Junji Yamamoto
发明人： Yoshitaka Taki , Kazuhiko Hata , Junji Yamamoto
IPC分类号： H04L700
CPC分类号： H04J3/0691 , H04J3/0688 , H04J2203/006 , H04J2203/0089
摘要： A synchronization message detecting unit detects a synchronization message from a line signal received from a line terminating unit. A synchronization message processing unit controls whether or not to select a clock reference received from the line as an active reference according to a quality level represented by the synchronization message. In this case, when an installed state detecting unit has determined that the synchronization message detecting unit has not been installed, the synchronization message processing unit does not select a clock reference corresponding to the synchronization message detected by the synchronization message detecting unit determined as a non-installed unit as the active reference.
摘要翻译：同步消息检测单元从从线路终端单元接收的线路信号检测同步消息。同步消息处理单元根据由同步消息表示的质量等级来控制是否选择从该线路接收到的时钟参考作为活动参考。在这种情况下，当安装状态检测单元已经确定同步消息检测单元尚未安装时，同步消息处理单元不选择与被确定为非同步消息检测单元的同步消息检测单元检测到的同步消息相对应的时钟参考安装的单元作为主动参考。

7. 发明授权

US6014414A Synchronization-message-based active reference switching unit 失效
标题翻译：基于同步消息的主动参考切换单元
公开(公告)号：US6014414A
公开(公告)日：2000-01-11
申请号：US824900
申请日：1997-03-26
申请人： Junji Yamamoto , Kazuhiko Hata , Yoshitaka Taki
发明人： Junji Yamamoto , Kazuhiko Hata , Yoshitaka Taki
IPC分类号： H04B10/032 , H04B10/077 , H04B10/079 , H04B10/27 , H04B10/275 , H04B10/556 , H04J3/00 , H04J3/06 , H04L7/00 , H04L12/42 , H04L12/43
CPC分类号： H04J3/0688 , H04J3/0638
摘要： A unit of the invention is installed in each of transmission units that make up a synchronous network. The unit selects from the clock references received an active reference that controls the operation of the corresponding transmission unit, based on the quality levels of clock references presented by synchronization messages received with the clock references. The clock references, each of which is selectable as the active reference, and their selection priorities are entered into a source priority list. By referencing the source priority list, the active reference is selected.
摘要翻译：本发明的单元安装在构成同步网络的每个传输单元中。该单元根据时钟参考所接收的同步消息所呈现的时钟参考的质量水平，从时钟参考中选择接收到控制相应传输单元的操作的有效参考。时钟参考，其中每一个可选择作为活动参考，其选择优先级被输入源优先级列表。通过引用源优先级列表，选择活动引用。

8. 发明授权

US06498794B1 Transmitter with cell switching function 失效
标题翻译：发射机具有小区切换功能
公开(公告)号：US06498794B1
公开(公告)日：2002-12-24
申请号：US09312995
申请日：1999-05-17
申请人： Keiichiro Tsukamoto , Yoshitaka Taki
发明人： Keiichiro Tsukamoto , Yoshitaka Taki
IPC分类号： H04L1256
CPC分类号： H04L49/606 , H04J3/1617 , H04L12/5601 , H04L2012/5675 , H04L2012/5684
摘要： A transmitter having an interface module to serve as an interface between ATM cells and synchronous frames. The interface module comprises a plurality of first physical paths for inputting ATM cells with channel identifiers given thereto to identify channels respectively; a second physical path for outputting a synchronous frame signal; a channel identifier inserter for inserting the channel identifiers, which are given to the first physical paths where the ATM cells are inputted, into predetermined areas of the ATM cells; and a mapper for mapping the multi-channel ATM cells with the channel identifiers inserted therein to one synchronous frame signal and outputting the same to the second physical path.
摘要翻译：具有用作ATM信元和同步帧之间接口的接口模块的发射机。接口模块包括用于输入ATM信元的多个第一物理路径，分配给它们的信道标识符分别标识信道; 用于输出同步帧信号的第二物理路径; 信道标识符插入器，用于将给予ATM信元的第一物理路径的信道标识符插入ATM信元的预定区域; 以及映射器，用于将插入其中的信道标识符的多信道ATM信元映射到一个同步帧信号，并将其输出到第二物理路径。

9. 发明授权

US5461345A Frequency synchronous circuit for reducing transition period from power on state to stable state 失效
标题翻译：频率同步电路，用于减少从接通状态到稳定状态的过渡期
公开(公告)号：US5461345A
公开(公告)日：1995-10-24
申请号：US187699
申请日：1994-01-27
申请人： Yoshitaka Taki
发明人： Yoshitaka Taki
IPC分类号： H03L7/00 , H03L7/06 , H03L7/097 , H03L7/10 , H04Q11/04
CPC分类号： H03L7/097 , H03L7/10 , H04J2203/006
摘要： A frequency synchronous circuit has a first selection unit, a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first selection unit is used to select one sampling signal from a first sampling signal having a first sampling time and a second sampling signal having a second sampling time shorter than the first sampling time. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during the sampling time of the selected one sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the selected one sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit. The comparison unit, which is connected to the storage/average unit and the second counter unit, is used to compare an output signal from the storage/average unit with an output signal from the second counter unit, and the frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of the comparison unit. Therefore, a transition period determined from a power ON state to a stable state can be reduced, and further, an original clock signal can be obtained and output by removing any noise components from a clock signal.
摘要翻译：频率同步电路具有第一选择单元，第一计数器单元，第二计数器单元，存储/平均单元和比较单元。第一选择单元用于从具有第一采样时间的第一采样信号和具有比第一采样时间短的第二采样时间的第二采样信号选择一个采样信号。第一计数器单元用于对所选择的一个采样信号的采样时间期间从频率同步电路外部提供的参考信号进行计数，并且第二计数器单元用于对从频率同步电路输出的同步时钟信号进行计数在所选择的一个采样信号的采样时间期间。可操作地连接到第一计数器单元的存储/平均单元用于存储和平均第一计数器单元的输出信号。连接到存储/平均单元和第二计数器单元的比较单元用于将来自存储/平均单元的输出信号与来自第二计数器单元的输出信号进行比较，并且频率同步电路输出同步时钟信号，其频率根据比较单元的输出信号而同步。因此，可以减少从电源接通状态到稳定状态所确定的过渡期，并且还可以通过从时钟信号中去除任何噪声分量来获得并输出原始时钟信号。

10. 发明授权

US5459435A Frequency synchronous circuit for obtaining original clock signal by removing noise components 失效
标题翻译：频率同步电路，通过去除噪声成分获得原始时钟信号
公开(公告)号：US5459435A
公开(公告)日：1995-10-17
申请号：US187102
申请日：1994-01-25
申请人： Yoshitaka Taki
发明人： Yoshitaka Taki
IPC分类号： H03L7/00 , H03L7/06 , H03L7/085 , H03L7/181
CPC分类号： H03L7/181 , H03L7/085
摘要： A frequency synchronous circuit has a first counter unit, a second counter unit, a storage/average unit, and a comparison unit. The first counter unit is used to count a reference signal supplied from outside the frequency synchronous circuit during a sampling time which is defined by a sampling signal, and the second counter unit is used to count a synchronous clock signal to be output from the frequency synchronous circuit during the sampling time of the sampling signal. The storage/average unit, which is operatively connected to the first counter unit, is used to store and average an output signal of the first counter unit. The comparison unit, which is connected to the storage/average unit and the second counter unit, is used to compare an output signal of the storage/average unit with an output signal of the second counter unit, and the frequency synchronous circuit outputs the synchronous clock signal whose frequency is synchronized in accordance with an output signal of the comparison unit. Therefore, an original clock signal can be obtained and output by removing noise components from a clock signal which may include the noise components.
摘要翻译：频率同步电路具有第一计数器单元，第二计数器单元，存储/平均单元和比较单元。第一计数器单元用于在由采样信号定义的采样时间期间对从频率同步电路外部提供的参考信号进行计数，并且第二计数器单元用于对从频率同步信号中输出的同步时钟信号进行计数采样时间采样信号的电路。可操作地连接到第一计数器单元的存储/平均单元用于存储和平均第一计数器单元的输出信号。连接到存储/平均单元和第二计数器单元的比较单元用于将存储/平均单元的输出信号与第二计数器单元的输出信号进行比较，并且频率同步电路输出同步时钟信号，其频率根据比较单元的输出信号而同步。因此，可以通过从可能包括噪声分量的时钟信号中去除噪声分量来获得并输出原始时钟信号。

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