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1. 发明授权

US08391040B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08391040B2
公开(公告)日：2013-03-05
申请号：US13052198
申请日：2011-03-21
申请人： Yoshinao Suzuki , Yuui Shimizu
发明人： Yoshinao Suzuki , Yuui Shimizu
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/04 , G11C16/06 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/30107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first memory chip, a second memory chip, and a control chip. The first chip includes a first inductor configured to transmit/receive a signal, and a memory cell. The second chip is disposed on the first chip and includes a second inductor configured to transmit/receive a signal, and a memory cell. The control chip includes a control circuit configured to control the first and second chips, and a third inductor configured to transmit/receive a signal to/from the first and second inductors. The outer peripheries of the first and second inductors are included in a closed space produced by extending the outer periphery of the third inductor in a direction perpendicular to a plane that includes the third inductor. The inductance of the third inductor is greater than at least one of the inductances of the first and second inductors.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一存储器芯片，第二存储器芯片和控制芯片。第一芯片包括被配置为发送/接收信号的第一电感器和存储器单元。第二芯片设置在第一芯片上，并且包括被配置为发送/接收信号的第二电感器和存储单元。控制芯片包括被配置为控制第一和第二芯片的控制电路和被配置为向/从第一和第二电感器发送/接收信号的第三电感器。第一和第二电感器的外围包括在通过使第三电感器的外周沿垂直于包括第三电感器的平面的方向延伸而产生的封闭空间。第三电感器的电感大于第一和第二电感器的电感中的至少一个。

2. 发明授权

US08797089B2 Voltage generator 有权
标题翻译：电压发生器
公开(公告)号：US08797089B2
公开(公告)日：2014-08-05
申请号：US13603800
申请日：2012-09-05
申请人： Yoshinao Suzuki
发明人： Yoshinao Suzuki
IPC分类号： G05F1/10
CPC分类号： G11C5/145 , G11C16/10 , G11C16/30
摘要： According to one embodiment, a voltage generator includes a step-up circuit and a limiter circuit. The step-up circuit outputs a first voltage to a first node. The limiter circuit includes first and second resistive elements, first and second capacitive elements, a switch element, and a comparator. The first resistive element is between the first node and a second node. The second resistive element is connected to the second node. The first capacitive element is between the first and second nodes. The switch element connects the second capacitive element to the second node at the same time that the first node is connected to a load. The comparator compares the potential at the second node with a reference potential.
摘要翻译：根据一个实施例，电压发生器包括升压电路和限幅器电路。升压电路将第一电压输出到第一节点。限幅器电路包括第一和第二电阻元件，第一和第二电容元件，开关元件和比较器。第一电阻元件在第一节点和第二节点之间。第二电阻元件连接到第二节点。第一电容元件在第一和第二节点之间。开关元件在第一节点连接到负载的同时将第二电容元件连接到第二节点。比较器比较第二节点处的电位与参考电位。

3. 发明授权

US07291318B2 Methods for manufacturing multi-wall carbon nanotubes 有权
标题翻译：制造多壁碳纳米管的方法
公开(公告)号：US07291318B2
公开(公告)日：2007-11-06
申请号：US10687805
申请日：2003-10-20
申请人： Yasunori Sakurabayashi , Takuya Kondo , Yasushi Yamazawa , Yoshinao Suzuki , Marc Monthioux , Mikako LE. Lay
发明人： Yasunori Sakurabayashi , Takuya Kondo , Yasushi Yamazawa , Yoshinao Suzuki , Marc Monthioux , Mikako LE. Lay
IPC分类号： D01F9/12 , B82B3/00
CPC分类号： B82Y30/00 , B82Y40/00 , C01B32/152 , C01B32/16 , C01B2202/02 , C01B2202/06 , C01B2202/34 , C01B2202/36 , Y10S977/844
摘要： A method is presented for effectively manufacturing multi-wall (double-wall, etc.) carbon nanotubes (CNTs) having a structure whereby interior tubes are formed within the CNTs. In this manufacturing method, fullerene/CNT hybrid structures are prepared, wherein assembled fullerenes, these being fullerenes that are linked, have been housed within single-wall CNTs. The interior tubes are formed from the assembled fullerenes by subjecting the hybrid structures to electron beam irradiation while in a heated state. It is preferred that irradiation with the electron beams occurs at a temperature of 100˜500° C. and with the electron beams having an accelerating voltage of 80˜250 kV. According to the manufacturing method of the present invention, multi-wall CNTs with few defects can be manufactured at lower temperatures and in a shorter period than in the case where the fullerene/CNT hybrid structures are only maintained under high temperature conditions (and electron beam irradiation is not performed).
摘要翻译：提出了一种用于有效地制造具有结构的多壁（双壁等）碳纳米管（CNT）的方法，其中内部管在CNT内形成。在该制造方法中，制备富勒烯/ CNT混合结构，其中组装的富勒烯（这些是连接的富勒烯）已经容纳在单壁CNT内。内部管由组装的富勒烯形成，通过在加热状态下对混合结构进行电子束照射。优选的是，电子束的照射在100〜500℃的温度下发生，电子束的加速电压为80〜250kV。根据本发明的制造方法，可以在较低的温度下和较短的时间内制造具有少量缺陷的多壁CNT，而不是富勒烯/ CNT复合结构仅保持在高温条件下（和电子束不进行照射）。

4. 发明授权

US5314659A Hard facing chromium-base alloys 失效
标题翻译：硬面铬基合金
公开(公告)号：US5314659A
公开(公告)日：1994-05-24
申请号：US883960
申请日：1992-05-15
申请人： Kensuke Hidaka , Kanichi Tanaka , Yoshio Kohira , Hideshi Yamaguchi , Yoshinao Suzuki , Masahiro Nakagawa , Yoshio Fuwa , Kazuhiko Mori , Yoshihiko Ito , Atsushi Taguchi
发明人： Kensuke Hidaka , Kanichi Tanaka , Yoshio Kohira , Hideshi Yamaguchi , Yoshinao Suzuki , Masahiro Nakagawa , Yoshio Fuwa , Kazuhiko Mori , Yoshihiko Ito , Atsushi Taguchi
IPC分类号： B23K35/30 , C22C19/05 , C22C27/06 , C22C30/00
CPC分类号： C22C27/06
摘要： A hard facing chromium-base alloy consisting essentially of 30.0 to 48.0% by weight of nickel, 1.5 to 15.0% by weight of tungsten and/or 1.0 to 6.5% by weight of molybdenum, the balance being more than 40.0% by weight of chromium, and the maximum sum of tungsten and molybdenum being 15.0% by weight. The alloy may also contain one or more of iron, cobalt, carbon, boron, aluminum, silicon, niobium and titanium. When the alloy is used in powder form as a material for hard facing by welding, the alloy may further contain 0.01 to 0.12% by weight of aluminum, yttrium, misch metal, titanium, zirconium and hafnium. 0.01 to 0.1% by weight of oxygen may also be added to the alloy. The alloy has a high degree of toughness, wear resistance and corrosion resistance. The alloy can be used as a hard facing material to be applied to various objects, such as automobile engine valves.
摘要翻译：基本上由30.0至48.0重量％的镍，1.5至15.0重量％的钨和/或1.0至6.5重量％的钼组成的硬质铬基合金，余量大于40.0重量％的铬，钨和钼的最大总和为15.0重量％。合金还可以含有铁，钴，碳，硼，铝，硅，铌和钛中的一种或多种。当合金以粉末形式用作通过焊接的硬面材料时，该合金还可以含有0.01至0.12重量％的铝，钇，混合金属，钛，锆和铪。也可以向合金中添加0.01〜0.1重量％的氧。该合金具有高韧性，耐磨性和耐腐蚀性。该合金可以用作用于各种物体的硬质材料，例如汽车发动机阀门。

5. 发明申请

US20130193944A1 VOLTAGE GENERATOR 有权
标题翻译：电压发生器
公开(公告)号：US20130193944A1
公开(公告)日：2013-08-01
申请号：US13603800
申请日：2012-09-05
申请人： Yoshinao SUZUKI
发明人： Yoshinao SUZUKI
IPC分类号： G05F1/10 , G11C16/04 , G11C16/06
CPC分类号： G11C5/145 , G11C16/10 , G11C16/30
摘要： According to one embodiment, a voltage generator includes a step-up circuit and a limiter circuit. The step-up circuit outputs a first voltage to a first node. The limiter circuit includes first and second resistive elements, first and second capacitive elements, a switch element, and a comparator. The first resistive element is between the first node and a second node. The second resistive element is connected to the second node. The first capacitive element is between the first and second nodes. The switch element connects the second capacitive element to the second node at the same time that the first node is connected to a load. The comparator compares the potential at the second node with a reference potential.
摘要翻译：根据一个实施例，电压发生器包括升压电路和限幅器电路。升压电路将第一电压输出到第一节点。限幅器电路包括第一和第二电阻元件，第一和第二电容元件，开关元件和比较器。第一电阻元件在第一节点和第二节点之间。第二电阻元件连接到第二节点。第一电容元件在第一和第二节点之间。开关元件在第一节点连接到负载的同时将第二电容元件连接到第二节点。比较器比较第二节点处的电位与参考电位。

6. 发明申请

US20120293243A1 SEMICONDUCTOR DEVICE INCLUDING BOOSTING CIRCUIT 审中-公开
标题翻译：包括升压电路的半导体器件
公开(公告)号：US20120293243A1
公开(公告)日：2012-11-22
申请号：US13427009
申请日：2012-03-22
申请人： Yoshinao Suzuki
发明人： Yoshinao Suzuki
IPC分类号： G05F3/02
CPC分类号： G11C5/145 , G11C16/30 , H01L27/0222
摘要： According to one embodiment, a semiconductor device includes the following configuration. A control circuit controls an output voltage to a predetermined voltage, based on a monitor voltage configured to monitor the output voltage. A switch circuit sets the output voltage to first and second voltages in first and second operation states, respectively. The second voltage is higher than the first voltage. A clock driver generates a clock signal that includes a voltage level of the output voltage as an amplitude thereof. A charge pump is formed by connecting unit circuits in series and at multiple stages. Each of the unit circuits includes a capacitor and a diode. The charge pump boosts an input voltage by the clock signal that is inputted to the capacitor.
摘要翻译：根据一个实施例，半导体器件包括以下配置。控制电路基于配置为监视输出电压的监视电压将输出电压控制到预定电压。开关电路分别在第一和第二操作状态下将输出电压设置为第一和第二电压。第二电压高于第一电压。时钟驱动器产生包括作为其幅度的输出电压的电压电平的时钟信号。电荷泵是通过串联连接多级连接而形成的。每个单元电路包括电容器和二极管。电荷泵通过输入到电容器的时钟信号来提升输入电压。

7. 发明申请

US20110267864A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110267864A1
公开(公告)日：2011-11-03
申请号：US13052198
申请日：2011-03-21
申请人： Yoshinao SUZUKI , Yuui SHIMIZU
发明人： Yoshinao SUZUKI , Yuui SHIMIZU
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/04 , G11C16/06 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/14 , H01L2924/30107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first memory chip, a second memory chip, and a control chip. The first chip includes a first inductor configured to transmit/receive a signal, and a memory cell. The second chip is disposed on the first chip and includes a second inductor configured to transmit/receive a signal, and a memory cell. The control chip includes a control circuit configured to control the first and second chips, and a third inductor configured to transmit/receive a signal to/from the first and second inductors. The outer peripheries of the first and second inductors are included in a closed space produced by extending the outer periphery of the third inductor in a direction perpendicular to a plane that includes the third inductor. The inductance of the third inductor is greater than at least one of the inductances of the first and second inductors.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一存储器芯片，第二存储器芯片和控制芯片。第一芯片包括被配置为发送/接收信号的第一电感器和存储器单元。第二芯片设置在第一芯片上，并且包括被配置为发送/接收信号的第二电感器和存储单元。控制芯片包括被配置为控制第一和第二芯片的控制电路和被配置为向/从第一和第二电感器发送/接收信号的第三电感器。第一和第二电感器的外围包括在通过使第三电感器的外周沿垂直于包括第三电感器的平面的方向延伸而产生的闭合空间。第三电感器的电感大于第一和第二电感器的电感中的至少一个。

8. 发明授权

US5425822A Hard facing chromium-base alloys 失效
标题翻译：硬面铬基合金
公开(公告)号：US5425822A
公开(公告)日：1995-06-20
申请号：US158982
申请日：1993-11-30
申请人： Kensuke Hidaka , Kanichi Tanaka , Yoshio Kohira , Hideshi Yamaguchi , Yoshinao Suzuki , Masahiro Nakagawa , Yoshio Fuwa , Kazuhiko Mori , Yoshihiko Ito , Atsushi Taguchi
发明人： Kensuke Hidaka , Kanichi Tanaka , Yoshio Kohira , Hideshi Yamaguchi , Yoshinao Suzuki , Masahiro Nakagawa , Yoshio Fuwa , Kazuhiko Mori , Yoshihiko Ito , Atsushi Taguchi
IPC分类号： B23K35/30 , C22C19/05 , C22C27/06 , C22C30/00
CPC分类号： C22C27/06
摘要： A hard facing chromium-base alloy consisting essentially of 30.0 to 48.0% by weight of nickel. 1.5 to 15.0% by weight of tungsten and/or 1.0 to 6.5% by weight of molybdenum, the balance being more than 40.0% by weight of chromium, and the maximum sum of tungsten and molybdenum being 15.0% by weight. The alloy may also contain one or more of iron, cobalt, carbon, boron, aluminum, silicon, niobium and titanium. When the alloy is used in powder form as a material for hard facing by welding, the alloy may further contain 0.01 to 0.12% by weight of aluminum, yttrium, misch metal, titanium, zirconium and hafnium. 0.01 to 0.1% by weight of oxygen may also be added to the alloy. The alloy has a high degree of toughness wear resistance and corrosion resistance. The alloy can be used as a hard facing material to be applied to various objects, such as automobile engine valves.
摘要翻译：基本上由30.0至48.0重量％的镍组成的硬质铬基合金。 1.5至15.0重量％的钨和/或1.0至6.5重量％的钼，余量大于40.0重量％的铬，钨和钼的最大总和为15.0重量％。合金还可以含有铁，钴，碳，硼，铝，硅，铌和钛中的一种或多种。当合金以粉末形式用作通过焊接的硬面材料时，该合金还可以含有0.01至0.12重量％的铝，钇，混合金属，钛，锆和铪。也可以向合金中添加0.01〜0.1重量％的氧。该合金具有高韧性耐磨性和耐腐蚀性。该合金可以用作用于各种物体的硬质材料，例如汽车发动机阀门。

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