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    • 3. 发明授权
    • Apparatus and method for testing electronic devices
    • 用于测试电子设备的装置和方法
    • US5289116A
    • 1994-02-22
    • US952469
    • 1992-09-28
    • Jun KuritaKiyoyasu HiwadaNobuyuki KasugaYoichiro YamadaShigeru KuwanoKeita GunjiTomoya Yamazaki
    • Jun KuritaKiyoyasu HiwadaNobuyuki KasugaYoichiro YamadaShigeru KuwanoKeita GunjiTomoya Yamazaki
    • G01R31/3167G01R31/319G01R31/3193G01R31/28
    • G01R31/3167G01R31/31922G01R31/3193
    • An apparatus 1 for testing mixed signal electronic devices (i.e., devices, such as LSI devices, whose input/output signals include direct current signals, digital signals and analog signals, where the time relationship between the various input and output signals may be either synchronous or asynchronous) includes a master clock subsystem (MCLK-SS) 11, a subsystem group comprised of a digital master subsystem (DM-SS) 12, a digital slave subsystem (DS-SS) 13, a waveform generator subsystem (WG-SS) 14, a waveform digitizer subsystem (WD-SS) 15, a time measuring module (TMM) 16, and a direct current subsystem (DC-SS) 17, and an interfacing test head 18. The MCLK-SS 11 receives a master clock from a timing generator 21 or DSP 23 of the device under test (DUT) 186 and generates a first master clock MCLK1 and a second master clock MCLK2, each of which is synchronized with the master clock from the DUT. A reference clock generator 111, which receives the output of the buffer 181, supplies a standard clock to the first and second clock generators 112, 113, which in turn generate the first and second master clock signals.
    • 一种用于测试混合信号电子装置(即诸如LSI装置的装置,其输入/输出信号包括直流信号,数字信号和模拟信号的装置1),其中各种输入和输出信号之间的时间关系可以是同步的 或异步)包括主时钟子系统(MCLK-SS)11,由数字主子系统(DM-SS)12,数字从属子系统(DS-SS)13,波形发生器子系统(WG-SS) )14,波形数字化器子系统(WD-SS)15,时间测量模块(TMM)16和直流子系统(DC-SS)17以及接口测试头18.MCLK-SS11接收主机 来自被测器件(DUT)186的定时发生器21或DSP 23的时钟,并且产生第一主时钟MCLK1和第二主时钟MCLK2,其中每一个与来自DUT的主时钟同步。 接收缓冲器181的输出的参考时钟发生器111将标准时钟提供给第一和第二时钟发生器112,113,第一和第二时钟发生器112,113又产生第一和第二主时钟信号。