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1. 发明申请

US20120214103A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH FINE PATTERNS 审中-公开
标题翻译：用精细图案制作半导体器件的方法
公开(公告)号：US20120214103A1
公开(公告)日：2012-08-23
申请号：US13030533
申请日：2011-02-18
申请人： Ming Kang Wei , Pei Lin Huang , Yi Ming Wang , Ying Chung Tseng
发明人： Ming Kang Wei , Pei Lin Huang , Yi Ming Wang , Ying Chung Tseng
IPC分类号： G03F7/20
CPC分类号： H01L21/31144 , G03F7/094 , G03F7/095 , H01L21/0274
摘要： A method for fabricating semiconductor devices with fine patterns includes the steps of providing a semiconductor substrate, forming a first photoresist layer on the semiconductor substrate, forming a second photoresist layer on the first photoresist layer, and performing an exposing process to change the state of at least one first portion of the first photoresist layer and the state of at least one second portion of the second photoresist layer. The conventional double patterning technique requires that the exposure processes be performed twice, which requires very precise alignment between the two exposure processes. In contrast, the embodiment of the present invention can perform the double patterning process with only one exposure process without requiring the precise alignment between the two exposure processes.
摘要翻译：用于制造具有精细图案的半导体器件的方法包括以下步骤：提供半导体衬底，在半导体衬底上形成第一光致抗蚀剂层，在第一光致抗蚀剂层上形成第二光致抗蚀剂层，以及执行曝光过程以改变第一光致抗蚀剂层的至少一个第一部分和第二光致抗蚀剂层的至少一个第二部分的状态。传统的双重图案化技术要求曝光过程进行两次，这需要两次曝光过程之间非常精确的对准。相反，本发明的实施例可以仅用一次曝光工艺进行双重图案化处理，而不需要两次曝光过程之间的精确对准。

2. 发明申请

US20100227069A1 APPARATUS FOR REDUCING COST OF DEVELOPER AND THE METHOD THEREOF 审中-公开
标题翻译：降低开发商成本的方法及其方法
公开(公告)号：US20100227069A1
公开(公告)日：2010-09-09
申请号：US12500995
申请日：2009-07-10
申请人： Chiang-Lin Shih , Pei-Lin Huang , Ying-Chung Tseng
发明人： Chiang-Lin Shih , Pei-Lin Huang , Ying-Chung Tseng
IPC分类号： B05D3/12 , B05D3/00 , B05C11/00
CPC分类号： H01L21/6715 , G03F7/3014 , G03F7/3021
摘要： An apparatus for homogenizing the developer concentration on the wafer and reducing the developer cost and the method thereof are provided in the present invention. The developer is provided on the wafer which then is spun to distribute the developer on the wafer. Next, the mechanical turbulence of the developer is produced on the wafer by the turbulence device or the mega-sonic vibrator. The apparatus is able to improve the uniformity of developer concentration, and the developer consumption is reduced.
摘要翻译：在本发明中提供了用于使晶片上的显影剂浓度均匀化并降低显影剂成本的装置及其方法。将显影剂提供在晶片上，然后旋转以将显影剂分布在晶片上。接下来，通过湍流装置或超声波振动器在晶片上产生显影剂的机械湍流。该装置能够提高显影剂浓度的均匀性，并且降低显影剂消耗。

3. 发明授权

US06833318B2 Gap-filling process 有权
标题翻译：间隙填充过程
公开(公告)号：US06833318B2
公开(公告)日：2004-12-21
申请号：US10065803
申请日：2002-11-20
申请人： Chun-Jen Weng , Juan-Yi Chen , Hong-Tsz Pan , Cedric Lee , Der-Yuan Wu , Jackson Lin , Yeong-Song Yen , Lawrence Lin , Ying-Chung Tseng
发明人： Chun-Jen Weng , Juan-Yi Chen , Hong-Tsz Pan , Cedric Lee , Der-Yuan Wu , Jackson Lin , Yeong-Song Yen , Lawrence Lin , Ying-Chung Tseng
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31144
摘要： A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.
摘要翻译：提供间隙填充过程。提供其上具有介电层的基板。电介质层中有一个开口。在电介质层和开口内部形成间隙填充材料层。间隙填充材料的一部分从间隙填充材料层去除以暴露电介质层。进行间隙填充材料层和电介质层的表面的间隙填充材料处理以使间隙填充材料层平坦化，从而在间隙填充材料上形成随后形成的底部抗反射涂层或材料层层可以具有高度的平面度。

4. 发明申请

US20110081618A1 LITHO-LITHO ETCH (LLE) DOUBLE PATTERNING METHODS 审中-公开
标题翻译： LITHO-LITHO ETCH（LLE）双重图案方法
公开(公告)号：US20110081618A1
公开(公告)日：2011-04-07
申请号：US12574650
申请日：2009-10-06
申请人： Yi-Ming Wang , Pei-Lin Huang , Ying-Chung Tseng
发明人： Yi-Ming Wang , Pei-Lin Huang , Ying-Chung Tseng
IPC分类号： G03F7/20
CPC分类号： G03F7/405 , G03F7/0035 , H01L21/0273
摘要： Litho-litho-etch double patterning (LLE-DP) methods using silylation freeze technology are presented. The LLE-DP method using a silylation freeze reaction comprises providing a substrate with a first photoresist layer thereon. A first exposure process is performed defining a first latent image in a first photoresist. The first patterned structures on the substrate is developed and baked for photo-generated acid diffusion. The photo-generated acid is reacted with a silylation agent to freeze the first patterned structures. A second photoresist layer is formed overlying the substrate. A second lithography process is performed to create second patterned structures on the substrate. The first patterned structures and the second patterned structures are interlaced each other.
摘要翻译：提出了使用甲硅烷基化冷冻技术的石墨蚀刻双重图案（LLE-DP）方法。使用甲硅烷基化冷冻反应的LLE-DP方法包括在其上提供其上具有第一光致抗蚀剂层的基底。执行在第一光致抗蚀剂中限定第一潜像的第一曝光处理。显影和烘烤基底上的第一图案结构用于光致酸扩散。将光产生的酸与甲硅烷基化剂反应以冷冻第一图案化结构。第二光致抗蚀剂层形成在衬底上。执行第二光刻工艺以在衬底上产生第二图案化结构。第一图案结构和第二图案结构彼此交错。

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