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1. 发明授权

US07000210B2 Adaptive adjustment of constraints during PLD placement processing 有权
标题翻译： PLD放置处理期间约束的自适应调整
公开(公告)号：US07000210B2
公开(公告)日：2006-02-14
申请号：US10288667
申请日：2002-11-05
申请人： Qinghong Wu , Yinan Shen
发明人： Qinghong Wu , Yinan Shen
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5054
摘要： A technique for mapping a plurality of configurable logic blocks in a programmable logic device, such as a field-programmable gate array (FPGA). The method includes adaptively adjusting one or more customer-specified constraints and can be implemented, for example, using a simulated annealing algorithm. During the refinement of the placement (i.e., assignment) of logic blocks in an FPGA, one or more constraints are adjusted by either selecting a customer-specified constraint value or specifying a new constraint value derived based on the actual circuit performance. The method provides substantial savings of computer time compared to the prior art placement methods and improves circuit performance, e.g., by enabling higher circuit operation frequencies.
摘要翻译：一种用于映射诸如现场可编程门阵列（FPGA）的可编程逻辑器件中的多个可配置逻辑块的技术。该方法包括自适应地调整一个或多个客户指定的约束，并且可以例如使用模拟退火算法来实现。在FPGA中对逻辑块的布局（即，分配）进行细化期间，通过选择客户指定的约束值或指定基于实际电路性能导出的新约束值来调整一个或多个约束。与现有技术的放置方法相比，该方法大大节省了计算机时间并且提高了电路性能，例如通过实现更高的电路工作频率。

2. 发明授权

US08086986B1 Clock boosting systems and methods 有权
标题翻译：时钟提升系统和方法
公开(公告)号：US08086986B1
公开(公告)日：2011-12-27
申请号：US12408047
申请日：2009-03-20
申请人： Yinan Shen , Song Xu
发明人： Yinan Shen , Song Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： In one embodiment of the invention, a programmable logic device (PLD) includes logic blocks, registers corresponding to the logic blocks, and configuration memory adapted to store configuration data for configuring the PLD. Also included in the PLD is a general routing network having a plurality of routing wires and a clock distribution network having a plurality of routing wires. At least one clock signal path is provided within the PLD from a clock source to one of the registers via a routing wire of the clock distribution network and a routing wire of the general routing network.
摘要翻译：在本发明的一个实施例中，可编程逻辑器件（PLD）包括逻辑块，对应于逻辑块的寄存器，以及适于存储用于配置PLD的配置数据的配置存储器。还包括在PLD中的是具有多个路由线的通用路由网络和具有多个路由选线的时钟分配网络。至少一个时钟信号路径通过时钟分配网络的路由选线和一般路由网络的路由选线从时钟源提供给寄存器之一。

3. 发明授权

US08112731B1 Congestion-driven placement systems and methods for programmable logic devices 有权
标题翻译：拥塞驱动放置系统和可编程逻辑器件的方法
公开(公告)号：US08112731B1
公开(公告)日：2012-02-07
申请号：US12277217
申请日：2008-11-24
申请人： Yinan Shen , Chih-Chung Chen , Bo Wang
发明人： Yinan Shen , Chih-Chung Chen , Bo Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Techniques are provided for reducing signal congestion in programmable logic devices (PLDs). In one example, a computer-implemented method of reducing signal congestion in a configuration of a PLD includes mapping a plurality of circuit components of a circuit design to a plurality of components of the PLD, wherein each of the mapped PLD components is associated with one of a plurality of regions of the PLD and with one or more unique signal paths entering the PLD region. The method also includes determining a cost value for each PLD region based at least in part on the number of unique signal paths entering the PLD region from other PLD regions. The method also includes selecting one of the PLD components to move from a first one of the PLD regions to a second one of the PLD regions. The method also includes updating the cost values associated with the first and second PLD regions based on a change in the number of unique signal paths entering the first and second PLD regions. The method also includes selectively accepting or rejecting the move based at least in part on the updated cost values.
摘要翻译：提供了用于减少可编程逻辑器件（PLD）中的信号拥塞的技术。在一个示例中，减少PLD的配置中的信号拥塞的计算机实现的方法包括将电路设计的多个电路组件映射到PLD的多个组件，其中映射的PLD组件中的每一个与一个的PLD的多个区域以及进入PLD区域的一个或多个唯一信号路径。该方法还包括至少部分地基于从其它PLD区域进入PLD区域的唯一信号路径的数量来确定每个PLD区域的成本值。该方法还包括选择一个PLD分量以从PLD区域中的第一个PLD区域移动到第二个PLD区域。该方法还包括基于进入第一和第二PLD区域的唯一信号路径的数量的变化来更新与第一和第二PLD区域相关联的成本值。该方法还包括至少部分地基于更新的成本值选择性地接受或拒绝移动。

4. 发明授权

US07509598B1 Clock boosting systems and methods 有权
标题翻译：时钟提升系统和方法
公开(公告)号：US07509598B1
公开(公告)日：2009-03-24
申请号：US11737702
申请日：2007-04-19
申请人： Yinan Shen , Song Xu
发明人： Yinan Shen , Song Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Systems and methods are disclosed herein to provide software clock boosting techniques. For example in one embodiment, a method of configuring a programmable logic device includes receiving routed data; performing a software clock boost operation on the routed data to determine and include one or more desired clock delays for circuit elements. The software clock boost operation may include performing a static timing analysis on the routed data; determining a list of the desired clock delays; and modifying the routed data to insert the desired clock delays.
摘要翻译：本文公开了提供软件时钟提升技术的系统和方法。例如在一个实施例中，配置可编程逻辑设备的方法包括接收路由数据; 对路由数据执行软件时钟提升操作以确定并包括用于电路元件的一个或多个期望的时钟延迟。软件时钟提升操作可以包括对路由数据执行静态时序分析; 确定期望的时钟延迟的列表; 并修改路由数据以插入所需的时钟延迟。

5. 发明授权

US06813754B2 Placement processing for programmable logic devices 有权
标题翻译：可编程逻辑器件的放置处理
公开(公告)号：US06813754B2
公开(公告)日：2004-11-02
申请号：US10288668
申请日：2002-11-05
申请人： Qinghong Wu , Yinan Shen , Liren Liu
发明人： Qinghong Wu , Yinan Shen , Liren Liu
IPC分类号： G06F1750
CPC分类号： G06F17/5054 , G06F17/5072
摘要： A method for placing configurable logic blocks (CLBs) in a PLD, such as an FPGA. In one embodiment, after packing gates/clusters into blocks and then assigning those blocks to CLBs to generate an initial placement, the packing and/or placement of CLBs is changed prior to performing CLB routing. For each node of the most critical of the K most critical paths in the initial placement, moving the node to a different CLB is considered in order to reduce the criticality of that path. A move is applied if certain acceptability conditions are met. After the most critical path is improved, the criticality of the K paths is updated, and the procedure is repeated for the new most critical of the K updated paths. The method, which can be automated to reduce human intervention in the design process, improves circuit performance, e.g., by enabling higher circuit operation frequencies.
摘要翻译：一种用于将可配置逻辑块（CLB）放置在诸如FPGA之类的PLD中的方法。在一个实施例中，在将门/集群封装成块之后，然后将这些块分配给CLB以产生初始放置，在执行CLB路由之前改变CLB的打包和/或放置。对于初始放置中最关键的K个关键路径的每个节点，考虑将节点移动到不同的CLB，以便降低该路径的临界性。如果满足某些可接受性条件，则应用移动。在最关键的路径得到改善之后，K路径的关键性被更新，并且对于K个更新的路径中最重要的新的重要路径重复该过程。该方法可以自动化以减少设计过程中的人为干预，从而提高电路性能，例如通过实现更高的电路工作频率。

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