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1. 发明授权

US08355081B2 Digital display control device and method thereof 有权
标题翻译：数字显示控制装置及其方法
公开(公告)号：US08355081B2
公开(公告)日：2013-01-15
申请号：US12055649
申请日：2008-03-26
申请人： Wen-Hsia Kung , Yu-Pin Chou , Yi-Teng Chen
发明人： Wen-Hsia Kung , Yu-Pin Chou , Yi-Teng Chen
IPC分类号： H03L7/00 , H04N9/475 , G06F3/038
CPC分类号： H04N5/04 , G09G5/008 , G09G5/12 , H04N5/126 , H04N5/50 , H04N21/4305 , H04N21/44016
摘要： The invention discloses a display control device and method thereof. The display control device and method thereof utilize the phase deviation and the frequency deviation between the output signal and the input signal caused during channel switching to provide converting time acceptable by a display device and to achieve the objective of balancing the data stream transmission.
摘要翻译：本发明公开了一种显示控制装置及其方法。显示控制装置及其方法利用在通道切换期间引起的输出信号和输入信号之间的相位偏差和频率偏差，提供显示装置可接受的转换时间，并实现平衡数据流传输的目的。

2. 发明申请

US20080239147A1 DIGITAL DISPLAY CONTROL DEVICE AND METHOD THEREOF 有权
标题翻译：数字显示控制装置及其方法
公开(公告)号：US20080239147A1
公开(公告)日：2008-10-02
申请号：US12055649
申请日：2008-03-26
申请人： Wen-Hsia KUNG , Yu-Pin CHOU , Yi-Teng CHEN
发明人： Wen-Hsia KUNG , Yu-Pin CHOU , Yi-Teng CHEN
IPC分类号： H04N5/06
CPC分类号： H04N5/04 , G09G5/008 , G09G5/12 , H04N5/126 , H04N5/50 , H04N21/4305 , H04N21/44016
摘要： The invention discloses a display control device and method thereof. The display control device and method thereof utilize the phase deviation and the frequency deviation between the output signal and the input signal caused during channel switching to provide converting time acceptable by a display device and to achieve the objective of balancing the data stream transmission.
摘要翻译：本发明公开了一种显示控制装置及其方法。显示控制装置及其方法利用在通道切换期间引起的输出信号和输入信号之间的相位偏差和频率偏差，提供显示装置可接受的转换时间，并实现平衡数据流传输的目的。

3. 发明授权

US07679454B2 Hybrid phase-locked loop 有权
标题翻译：混合锁相环
公开(公告)号：US07679454B2
公开(公告)日：2010-03-16
申请号：US11874209
申请日：2007-10-18
申请人： Chi-Kung Kuan , Yu-Pin Chou , Yi-Teng Chen
发明人： Chi-Kung Kuan , Yu-Pin Chou , Yi-Teng Chen
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/081 , H03L7/1976 , H03L7/23
摘要： A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an input signal and a feedback signal. The digital loop filter generates a first control signal according to the first detection signal. The decision circuit generates a divisor value according to the first control signal. The fractional-N PLL generates an oscillation signal according to the divisor value and a reference signal. The frequency divider divides the oscillation signal to produce the feedback signal. The fractional-N PLL includes a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.
摘要翻译：提供了包括数字PFD，数字环路滤波器，判决电路，分数N PLL和分频器的锁相环（PLL）。数字PFD根据输入信号和反馈信号之间的相位误差或频率差产生第一检测信号。数字环路滤波器根据第一检测信号产生第一控制信号。决定电路根据第一控制信号产生除数值。分数N PLL根据除数值和参考信号产生振荡信号。分频器分频振荡信号产生反馈信号。分数N PLL包括分数N分频器，用于通过采用相位吞吐装置，根据除数值产生用于跟踪参考信号的分频信号。

4. 发明申请

US20080094145A1 HYBRID PHASE-LOCKED LOOP 有权
标题翻译：混合锁相环
公开(公告)号：US20080094145A1
公开(公告)日：2008-04-24
申请号：US11874209
申请日：2007-10-18
申请人： Chi-Kung Kuan , Yu-Pin Chou , Yi-Teng Chen
发明人： Chi-Kung Kuan , Yu-Pin Chou , Yi-Teng Chen
IPC分类号： H03L7/087 , H03L7/00
CPC分类号： H03L7/087 , H03L7/081 , H03L7/1976 , H03L7/23
摘要： A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an input signal and a feedback signal. The digital loop filter generates a first control signal according to the first detection signal. The decision circuit generates a divisor value according to the first control signal. The fractional-N PLL generates an oscillation signal according to the divisor value and a reference signal. The frequency divider divides the oscillation signal to produce the feedback signal. The fractional-N PLL includes a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.
摘要翻译：提供了包括数字PFD，数字环路滤波器，判决电路，分数N PLL和分频器的锁相环（PLL）。数字PFD根据输入信号和反馈信号之间的相位误差或频率差产生第一检测信号。数字环路滤波器根据第一检测信号产生第一控制信号。决定电路根据第一控制信号产生除数值。分数N PLL根据除数值和参考信号产生振荡信号。分频器分频振荡信号产生反馈信号。分数N PLL包括分数N分频器，用于通过采用相位吞吐装置，根据除数值产生用于跟踪参考信号的分频信号。

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