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    • 1. 发明授权
    • High-speed serial link clock and data recovery
    • 高速串行链路时钟和数据恢复
    • US07415089B2
    • 2008-08-19
    • US10800653
    • 2004-03-16
    • Chau-chin SuChien-Hsi LeeHung-Wen LuHsueh-Chin LinYen-Pin TsengChia-Nan WangUan-Jiun Liu
    • Chau-chin SuChien-Hsi LeeHung-Wen LuHsueh-Chin LinYen-Pin TsengChia-Nan WangUan-Jiun Liu
    • H04L7/00
    • H04L7/0338H04L7/005
    • A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.
    • 时钟和数据恢复系统(“CDR”)包括时钟发生器,用于接收输入数据的半速率相位检测器,编码器,输出恢复时钟的相位选择器,置信计数器和输出恢复数据的多路复用器。 时钟发生器以传输的串行数据的一半速率产生8相时钟信号。 相位检测器以标准采样速率的四倍采样输入数据,采用过采样数据并检测其中的相位变化,即相位超前和滞后。 编码器对相变数据进行编码。 置信计数器接收相变数据,并产生表示相变的累积净效应的信号。 相位选择器从时钟发生器接收置信计数器信号和8相时钟,并确定数据采样的最佳相位。
    • 3. 发明申请
    • High-speed serial link clock and data recovery
    • 高速串行链路时钟和数据恢复
    • US20050207520A1
    • 2005-09-22
    • US10800653
    • 2004-03-16
    • Chau-chin SuChien-Hsi LeeHung-Wen LuHsueh-Chin LinYen-Pin TsengChia-Nan WangUan-Jiun Liu
    • Chau-chin SuChien-Hsi LeeHung-Wen LuHsueh-Chin LinYen-Pin TsengChia-Nan WangUan-Jiun Liu
    • H04L7/00H04L7/033
    • H04L7/0338H04L7/005
    • A system for clock and data recovery (“CDR”) includes a clock generator, a half-rate phase detector for receiving the input data, an encoder, a phase selector outputting recovered clock, a confidence counter, and a multiplexer outputting recovered data. The clock generator generates an 8-phase clock signal at half a rate of the transmitted serial data. The phase detector samples input data at four times the standard sampling rate, takes the oversampled data and detects phase transitions therein, i.e., phase lead and lag. The encoder encodes the phase transition data. The confidence counter receives the phase transition data and generates a signal representing the accumulated net effect of the phase transitions. The phase selector receives the confidence counter signal and the 8-phase clock from the clock generator, and determines the optimum phase for data sampling.
    • 时钟和数据恢复系统(“CDR”)包括时钟发生器,用于接收输入数据的半速率相位检测器,编码器,输出恢复时钟的相位选择器,置信计数器和输出恢复数据的多路复用器。 时钟发生器以传输的串行数据的一半速率产生8相时钟信号。 相位检测器以标准采样速率的四倍采样输入数据,采用过采样数据并检测其中的相位变化,即相位超前和滞后。 编码器对相变数据进行编码。 置信计数器接收相变数据,并产生表示相变的累积净效应的信号。 相位选择器从时钟发生器接收置信计数器信号和8相时钟,并确定数据采样的最佳相位。