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2. 发明授权

US4686686A Line equalizer operable in response to an input signal of a variable data rate 失效
标题翻译：线路均衡器响应于可变数据速率的输入信号而可操作
公开(公告)号：US4686686A
公开(公告)日：1987-08-11
申请号：US772538
申请日：1985-09-04
申请人： Kenji Nakayama , Yayoi Takeuchi
发明人： Kenji Nakayama , Yayoi Takeuchi
IPC分类号： H03H19/00 , H04B3/14 , H04L25/03 , H04L25/04 , H03K5/159
CPC分类号： H04L25/03019
摘要： In a line equalizer responsive to an input signal of a variable data rate for producing an equalizer output signal, a control circuit (12) supplies an equalizer circuit (11) with a selection signal (SEL) which is determined by the data rate and an output level of the equalizer output signal to select a frequency-gain characteristic that is matched with the line loss characteristic of a line. The equalizer circuit is implemented by a switched capacitor circuit and samples the input signal via a clock signal (CK) a clock frequency of which is varied by a clock signal controller (51) in consideration of the data rate. An additional equalizer circuit may be connected in cascade to the equalizer circuit and controlled by an additional control signal determined by the data rate and the output level. In this event, the selection signal may be determined only by the output level with the clock signal left out of consideration.
摘要翻译：在响应于用于产生均衡器输出信号的可变数据速率的输入信号的行均衡器中，控制电路（12）向均衡器电路（11）提供由数据速率确定的选择信号（SEL），并且输出电平，以选择与线路的线路损耗特性匹配的频率增益特性。均衡器电路由开关电容器电路实现，并且通过考虑到数据速率的时钟信号控制器（51）改变的时钟频率的时钟信号（CK）对输入信号进行采样。附加的均衡器电路可以级联连接到均衡器电路并由由数据速率和输出电平确定的附加控制信号控制。在这种情况下，选择信号可以仅由考虑的时钟信号的输出电平确定。

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