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1. 发明申请

WO1995022146A1 SEMICONDUCTOR CIRCUIT 审中-公开
标题翻译：半导体电路
公开(公告)号：WO1995022146A1
公开(公告)日：1995-08-17
申请号：PCT/JP1995000204
申请日：1995-02-14
申请人： SHIBATA, Tadashi , OHMI, Tadahiro , YAMASHITA, Takeo
IPC分类号： G11C27/00
CPC分类号： G11C27/005 , G11C7/16 , G11C11/54 , G11C11/5621 , G11C2211/5611
摘要： This invention provides a semiconductor circuit which can fetch and store analog and multilevel data by using a simple circuit. This invention also provides a multilevel memory which can freely change the number of quantizing levels by using external signals. The semiconductor circuit comprises a first circuit which converts first signals into a group of quantized signals, a second circuit which converts the signal group into second multilevel signals, and means which feeds back the second signals to the first circuit as first signals. The semiconductor circuit further has a means which electrically separates at least one signal included in the signal group from the input of the second circuit, and a means which feeds back the second signals to the input of the second circuit instead of the signal separated.
摘要翻译：本发明提供一种半导体电路，其可以通过使用简单的电路来获取和存储模拟和多电平数据。本发明还提供一种可以通过使用外部信号自由地改变量化电平数量的多电平存储器。半导体电路包括将第一信号转换成一组量化信号的第一电路，将信号组转换为第二多电平信号的第二电路，以及将第二信号作为第一信号反馈到第一电路的装置。半导体电路还具有将信号组中包括的至少一个信号与第二电路的输入电隔离的装置，以及将第二信号反馈到第二电路的输入而不是分离信号的装置。

2. 发明申请

WO1995018488A1 SEMICONDUCTOR CIRCUIT 审中-公开
标题翻译：半导体电路
公开(公告)号：WO1995018488A1
公开(公告)日：1995-07-06
申请号：PCT/JP1994002258
申请日：1994-12-27
申请人： SHIBATA, Tadashi , OHMI, Tadahiro , YAMASHITA, Takeo
IPC分类号： H03K03/3568
CPC分类号： G06N3/0635 , G11C27/005 , H03K3/3568 , H03M1/36 , H03M1/802
摘要： A simple semiconductor circuit by which analog data or multilevel data can be fetched and stored. The circuit receives a first signal and converts the first signal into a second signal composed of multilevel. The second signal is fed back to the circuit. The circuit is constituted of a first circuit which converts the first signal into a signal group composed of multiple quantized signals and second circuit which converts the signal group into the second signal. In addition, the first or/and second circuits are constituted of one or more neuron MOS transistors.
摘要翻译：一种简单的半导体电路，通过该电路可以获取和存储模拟数据或多级数据。电路接收第一信号并将第一信号转换成由多电平组成的第二信号。第二个信号被反馈回电路。电路由将第一信号转换为由多个量化信号组成的信号组的第一电路和将信号组转换为第二信号的第二电路构成。此外，第一或/和第二电路由一个或多个神经元MOS晶体管构成。

3. 发明申请

WO1995017008A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO1995017008A1
公开(公告)日：1995-06-22
申请号：PCT/JP1994002118
申请日：1994-12-16
申请人： OHMI, Tadahiro , YAMASHITA, Takeo , NAKAMURA, Yoshio
IPC分类号： H01L21/82
CPC分类号： H01L27/112
摘要： A semiconductor device capable of storing data after fabrication of an IC chip and capable of high speed readout, such as very large-scale integration ROMs. A semiconductor device including at least one semiconductor element comprising first and second conductor regions, either one or both, of which are made of metal, and a high resistance semiconductor region sandwiched between the first and second conductor regions, wherein a current is supplied to the high resistance semiconductor region through the first and second conductor regions, and/or heat is applied from outside, so that the reaction takes place between the metallic conductor region, either the first or second region, and the high resistance region to form a metallic semiconductor compound having low resistance.
摘要翻译：能够在制造IC芯片之后存储数据并且能够高速读出的半导体器件，例如非常大规模的集成ROM。一种半导体器件，包括至少一个半导体元件，该半导体元件包括由金属制成的第一和第二导体区域，以及夹在第一和第二导体区域之间的高电阻半导体区域，其中电流被提供给通过第一和第二导体区域的高电阻半导体区域和/或从外部施加热量，使得反应发生在第一或第二区域的金属导体区域与高电阻区域之间，以形成金属半导体化合物具有低电阻。

4. 发明申请

WO1993004210A1 METHOD FOR FORMING OXIDE FILM 审中-公开
标题翻译：形成氧化膜的方法
公开(公告)号：WO1993004210A1
公开(公告)日：1993-03-04
申请号：PCT/JP1992001048
申请日：1992-08-19
申请人： OHMI, Tadahiro , IMAOKA, Takashi; , SHIMADA, Hisayuki; , KONISHI, Nobuhiro; , MORITA, Mizuho; , YAMASHITA, Takeo; , SHIBATA, Tadashi; , WAKAMATSU, Hidetoshi; , WATANABE, Jinzo; , AOYAMA, Shintaro; , NAKAMURA, Masakazu;
IPC分类号： C23C08/10
CPC分类号： H01L21/02052 , C23C8/10 , C23C8/36 , C23C14/021 , C23C14/022 , C23C14/48 , C23C14/564 , C23C16/02 , C23C16/4401 , C30B23/02 , C30B25/02 , C30B29/16 , H01L21/02238 , H01L21/02255 , H01L21/31612
摘要： Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressures in the vessels are reducible respectively. The vessels are so configured that objects to be processed are movable among them, and there is provided light projection means for projecting ultraviolet rays on gases introduced to at least one of the vessels.
摘要翻译：真空处理设备能够防止颗粒粘附在真空容器中被处理物体。真空设备包括一系列由门分离的真空容器，容器中的压力分别可以减少。容器的构造使得待加工物体可以在其间移动，并且设置有用于将紫外线投射到引入到至少一个容器的气体的光投射装置。

5. 发明申请

WO1995022201A1 SEMICONDUCTOR CIRCUIT 审中-公开
标题翻译：半导体电路
公开(公告)号：WO1995022201A1
公开(公告)日：1995-08-17
申请号：PCT/JP1995000205
申请日：1995-02-14
申请人： SHIBATA, Tadashi , OHMI, Tadahiro , YAMASHITA, Takeo
IPC分类号： H03K05/08
CPC分类号： G06N3/0635
摘要： A semiconductor circuit which can not only store analog data and multilevel data by using a simple circuit, but also compare inputted data with stored data. The circuit stores a first signal, and when the difference between the magnitude of a second signal and that of the first signal stored is smaller or larger than a prescribed first value, outputs a prescribed second value. The circuit is constituted of multiple neuron MOS transistors each of which has, on a substrate (1), a semiconductor region of one conductivity type, source and drain regions of the opposite conductivity type formed in the semiconductor region, floating gate electrode which is provided in an area separating the source and drain regions from each other through an insulating film and is in a potentially floating state, and multiple input gate electrodes which are capacitance-coupled with the floating gate electrode through the insulating film.
摘要翻译：一种半导体电路，其不仅可以通过使用简单的电路存储模拟数据和多电平数据，而且还将输入的数据与存储的数据进行比较。电路存储第一信号，并且当第二信号的幅度与存储的第一信号的幅度之差小于或大于规定的第一值时，输出规定的第二值。电路由多个神经元MOS晶体管构成，每个神经元MOS晶体管在基板（1）上具有一个导电类型的半导体区域，形成在半导体区域中的相反导电类型的源极和漏极区域，设置有浮置栅电极在通过绝缘膜将源极和漏极区彼此分离并且处于潜在浮动状态的区域中，以及通过绝缘膜与浮置栅极电容耦合的多个输入栅电极。

6. 发明申请

WO1995015580A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO1995015580A1
公开(公告)日：1995-06-08
申请号：PCT/JP1994002000
申请日：1994-11-29
申请人： OHMI, Tadahiro , SHIBATA, Tadashi , KOSAKA, Hideo , YAMASHITA, Takeo
IPC分类号： H01L29/788
CPC分类号： G11C27/005 , G06N3/063 , G06N3/0635 , H01L29/42324 , H01L29/7881
摘要： Synapse can be formed from a smaller number of elements in a low-power semiconductor device, which realize a highly integrated neural network. Precise modifications of synapse weighting becomes possible and a neuron computer chip of a practical level can be accomplished. The semiconductor device includes a first electrode for charge injection, connected to a floating gate through a first insulating film; a second electrode for applying programming pulses, connected to the floating gate through a second insulating film; and a MOS transistor using the floating gate as its gate electrode, wherein the charge supplied from the source electrode of the MOS transistor sets the potential at the first electrode to a predetermined value determined by the potential of the floating gate, and charges are transferred between the floating gate and the first electrode through the first insulating film by applying a predetermined pulsating voltage to the second electrode.
摘要翻译：突触可以由低功率半导体器件中的较少数量的元件形成，这实现了高度集成的神经网络。突变加权的精确修改成为可能，并且可以实现实用水平的神经元计算机芯片。半导体器件包括用于电荷注入的第一电极，通过第一绝缘膜连接到浮置栅极; 用于施加编程脉冲的第二电极，通过第二绝缘膜连接到浮置栅极; 以及使用浮置栅极作为其栅电极的MOS晶体管，其中从MOS晶体管的源极提供的电荷将第一电极处的电位设置为由浮置栅极的电位确定的预定值，并且电荷在所述浮置栅极和所述第一电极通过对所述第二电极施加预定的脉动电压而穿过所述第一绝缘膜。

7. 发明申请

WO1994019760A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO1994019760A1
公开(公告)日：1994-09-01
申请号：PCT/JP1994000262
申请日：1994-02-22
申请人： SHIBATA, Tadashi , OHMI, Tadahiro , YAMASHITA, Takeo
IPC分类号： G06G07/60
CPC分类号： G06F7/24 , G06N3/0635
摘要： A device comprising invertor circuit group including two or more invertor circuits formed by neuron MOS transistors; means for applying a first signal voltage common to the two or more invertors of the invertor circuit group to a first input gate of the invertor circuits; means for applying a given second signal to one or more second input gates other than the first input gate of the invertor circuits; a delay circuit for transmitting the variation of the output voltage of at least one of the invertor circuits of the invertor circuit group with a time delay generated by use of the variation with time of the signal voltage of either or both of the first and second signal voltages; a transistor whose ON and OFF is controlled by the signal transmitted from the delay circuit; storage circuits taking in signals by the ON and OFF of the transistor; and means for executing a given logical operation with respect to the output voltage signals generated by the invertor circuit group. The device has a function of storing the result of the logical operation in the storage circuits.
摘要翻译：一种包括由神经元MOS晶体管形成的包括两个或更多个反相器电路的逆变器电路组的器件; 用于将所述逆变器电路组的两个或更多个反相器公共的第一信号电压施加到所述逆变器电路的第一输入门的装置; 用于将给定的第二信号施加到除了逆变器电路的第一输入门之外的一个或多个第二输入门的装置; 延迟电路，用于通过使用随着第一和第二信号中的任一个或第二信号的信号电压随时间的变化而产生的时间延迟来发送反相器电路组的至少一个反相器电路的输出电压的变化电压; 晶体管的ON和OFF由从延迟电路发送的信号控制; 存储电路通过晶体管的导通和截止来接收信号; 以及用于对由逆变器电路组产生的输出电压信号执行给定逻辑运算的装置。该装置具有将逻辑运算的结果存储在存储电路中的功能。

8. 发明申请

WO1984003984A1 MAGNETIC HEAD AND METHOD OF MANUFACTURE THEREOF 审中-公开
标题翻译：磁头及其制造方法
公开(公告)号：WO1984003984A1
公开(公告)日：1984-10-11
申请号：PCT/JP1984000159
申请日：1984-04-02
申请人： HITACHI, LTD. , KUMASAKA, Noriyuki , FUJIWARA, Hideo , OHTOMO, Shigekazu , YAMASHITA, Takeo , SAITO, Noritoshi , KUDO, Mitsuhiro
发明人： HITACHI, LTD.
IPC分类号： G11B05/27
CPC分类号： G11B5/2651 , G11B5/2655
摘要： A magnetic head which enables the formation of a guard band on a magnetic recording medium, and which is particularly suitable for a magnetic disk, is disclosed together with a method of manufacturing thereof. The magnetic head is provided with a recording/reproducing head core (31) and an erasure head core (32) which is also used for forming a guard band, and which is integrally bonded in series to the head core (31). A magnetic circuit is constituted by magnetic metal members (34), (34'), (35), (35') formed on non-magnetic members (33), (33'). It is possible to record on a recording medium with a high coercive force and reduce the track width, and this magnetic head is highly accurate and easy to manufacture.

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