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1. 发明申请

WO1998059291A1 METHOD OF CONTROL OF MEMORY CONTROLLER 审中-公开
标题翻译：记忆控制器的控制方法
公开(公告)号：WO1998059291A1
公开(公告)日：1998-12-30
申请号：PCT/JP1997002135
申请日：1997-06-20
申请人： HITACHI, LTD. , YAMAGAMI, Kenji , YAMAMOTO, Akira
发明人： HITACHI, LTD.
IPC分类号： G06F03/06
CPC分类号： G06F12/0866
摘要： One or more memory-device-side processors which can access the memory device belong to one group. Common memories and cache memories are allotted to the respective groups. When the access to the memory device is requested by a host-side processor, the memory-device-side processor of the group to which the memory device belongs informs the host-side processor of the stored cache address or the cache address to be stored and the data length. The host-side processor reads data at the address or writes data into the address. Thus, the access neck of the common memory and the cache memory is reduced and the system throughput is improved.
摘要翻译：可以访问存储器件的一个或多个存储器件侧处理器属于一个组。公共存储器和高速缓存存储器被分配给各个组。当由主机侧处理器请求对存储器件的访问时，存储器件所属的组的存储器件侧处理器通知主机侧处理器存储的高速缓存地址或要存储的高速缓存地址和数据长度。主机侧处理器在地址处读取数据或将数据写入地址。因此，公共存储器的访问颈部和高速缓冲存储器被减少，并且提高了系统吞吐量。

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