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1. 发明授权

US10297315B2 Resistive memory accelerator 有权
公开(公告)号：US10297315B2
公开(公告)日：2019-05-21
申请号：US15657288
申请日：2017-07-24
申请人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
发明人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
IPC分类号： G11C13/00 , G11C7/16
摘要： Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

2. 发明申请

US20180068722A1 RESISTIVE MEMORY ACCELERATOR 审中-公开
公开(公告)号：US20180068722A1
公开(公告)日：2018-03-08
申请号：US15801372
申请日：2017-11-02
申请人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
发明人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
IPC分类号： G11C13/00 , G11C7/16
CPC分类号： G11C13/004 , G11C7/16 , G11C13/0002 , G11C13/0069
摘要： Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

3. 发明授权

US08874827B2 Page merging for buffer efficiency in hybrid memory systems 有权
标题翻译：页面合并混合内存系统中的缓冲效率
公开(公告)号：US08874827B2
公开(公告)日：2014-10-28
申请号：US13453919
申请日：2012-04-23
申请人： Xiaochen Guo , Arun Jagatheesan
发明人： Xiaochen Guo , Arun Jagatheesan
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06
CPC分类号： G06F12/0638 , G06F12/0246
摘要： In a first embodiment of the present invention, a method for managing memory in a hybrid memory system is provided, wherein the hybrid memory system has a first memory and a second memory, wherein the first memory is smaller than the second memory and the first and second memories are of different types, the method comprising: identifying two or more pages in the first memory that are compatible with each other based at least in part on a prediction of when individual blocks within each of the two or more pages will be accessed; merging the two or more compatible pages, producing a merged page; and storing the merged page in the first memory.
摘要翻译：在本发明的第一实施例中，提供了一种用于管理混合存储器系统中的存储器的方法，其中所述混合存储器系统具有第一存储器和第二存储器，其中所述第一存储器小于所述第二存储器，第二存储器是不同类型的，所述方法包括：至少部分地基于对所述两个或多个页面中的每一个内的各个块何时被访问的预测来识别所述第一存储器中彼此兼容的两个或更多个页面; 合并两个或多个兼容页面，生成合并页面; 并将合并的页面存储在第一存储器中。

4. 发明授权

US09847125B2 Resistive memory accelerator 有权
公开(公告)号：US09847125B2
公开(公告)日：2017-12-19
申请号：US15229818
申请日：2016-08-05
申请人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
发明人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
IPC分类号： G11C13/00 , G11C7/16
CPC分类号： G11C13/004 , G11C7/16 , G11C13/0002 , G11C13/0069
摘要： Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

5. 发明授权

US10261977B2 Resistive memory accelerator 有权
公开(公告)号：US10261977B2
公开(公告)日：2019-04-16
申请号：US15587024
申请日：2017-05-04
申请人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
发明人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
IPC分类号： G11C11/00 , G06F17/16 , G06F3/06 , G06F17/11 , G11C7/10 , G11C11/16 , G11C13/00
摘要： A method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

6. 发明申请

US20180322094A1 RESISTIVE MEMORY ACCELERATOR 审中-公开
公开(公告)号：US20180322094A1
公开(公告)日：2018-11-08
申请号：US15587024
申请日：2017-05-04
申请人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
发明人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
IPC分类号： G06F17/16 , G06F3/06 , G11C11/16 , G11C13/00 , G11C11/56 , G06F17/11
CPC分类号： G06F17/16 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G06F17/11 , G11C7/1006 , G11C11/161 , G11C13/0004 , G11C13/0007
摘要： Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

7. 发明申请

US20170330617A1 RESISTIVE MEMORY ACCELERATOR 审中-公开
公开(公告)号：US20170330617A1
公开(公告)日：2017-11-16
申请号：US15657288
申请日：2017-07-24
申请人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
发明人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
IPC分类号： G11C13/00 , G11C7/16
CPC分类号： G11C13/004 , G11C7/16 , G11C13/0002 , G11C13/0069
摘要： Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

8. 发明申请

US20170040054A1 RESISTIVE MEMORY ACCELERATOR 有权
标题翻译：电阻记忆加速器
公开(公告)号：US20170040054A1
公开(公告)日：2017-02-09
申请号：US15229818
申请日：2016-08-05
申请人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
发明人： Eby Friedman , Isaac Richter , Xiaochen Guo , Mohammad Kazemi , Kamil Pas , Ravi Patel , Engin Ipek , Ji Liu
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/16 , G11C13/0002 , G11C13/0069
摘要： Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.
摘要翻译：提出了一种解决方法和装置。该方法包括通过电阻式存储器阵列接收第一数据，该电阻存储器阵列包括多个单元，其中所述接收包括在所述多个单元上设置多个电阻，其中所述多个电阻中的每一个基于第一个数据。该方法还包括由电阻式存储器阵列接收第二数据，其中接收包括在多个单元上施加基于第二数据的电流和电压中的至少一个。该方法还包括由电阻式存储器阵列确定基于第一数据和第二数据的初始未知值，初始值。

9. 发明申请

US20130042059A1 PAGE MERGING FOR BUFFER EFFICIENCY IN HYBRID MEMORY SYSTEMS 有权
标题翻译：混合存储系统中缓冲效率的页面合并
公开(公告)号：US20130042059A1
公开(公告)日：2013-02-14
申请号：US13453919
申请日：2012-04-23
申请人： Xiaochen Guo , Arun Jagatheesan
发明人： Xiaochen Guo , Arun Jagatheesan
IPC分类号： G06F12/02
CPC分类号： G06F12/0638 , G06F12/0246
摘要： In a first embodiment of the present invention, a method for managing memory in a hybrid memory system is provided, wherein the hybrid memory system has a first memory and a second memory, wherein the first memory is smaller than the second memory and the first and second memories are of different types, the method comprising: identifying two or more pages in the first memory that are compatible with each other based at least in part on a prediction of when individual blocks within each of the two or more pages will be accessed; merging the two or more compatible pages, producing a merged page; and storing the merged page in the first memory.
摘要翻译：在本发明的第一实施例中，提供了一种用于管理混合存储器系统中的存储器的方法，其中所述混合存储器系统具有第一存储器和第二存储器，其中所述第一存储器小于所述第二存储器，第二存储器是不同类型的，所述方法包括：至少部分地基于对两个或更多个页面中的每一个内的单个块将被访问的预测来识别第一存储器中彼此兼容的两个或更多个页面; 合并两个或多个兼容页面，生成合并页面; 并将合并的页面存储在第一存储器中。

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