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1. 发明申请

US20090198867A1 METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE EFFICIENT STORE QUEUE USAGE 有权
标题翻译：用于链接更多有效存储队列使用的多个小型存储队列的方法
公开(公告)号：US20090198867A1
公开(公告)日：2009-08-06
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译：数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。响应于第一段不等于第二段，第一个条目链接到第二个条目。

2. 发明授权

US06668332B1 Functional clock observation controlled by JTAG extensions 有权
标题翻译：功能时钟观察由JTAG扩展控制
公开(公告)号：US06668332B1
公开(公告)日：2003-12-23
申请号：US09504367
申请日：2000-02-15
申请人： William Lloyd McNeil
发明人： William Lloyd McNeil
IPC分类号： G06F100
CPC分类号： G01R31/31725 , G01R31/318552 , G06F1/22
摘要： Internal clock signals generated on a chip can be viewed externally by multiplexing the clock signals and functional output signals to pin that are used to view or access the functional output signals. JTAG facilities already provided on the chip are used to generate control signals that drive the multiplexers. By so doing no new input or output facilities are required to view the clock signals.
摘要翻译：通过将时钟信号和功能输出信号复用为用于查看或访问功能输出信号的引脚，可以在外部查看芯片上产生的内部时钟信号。已经在芯片上提供的JTAG设备用于产生驱动多路复用器的控制信号。通过这样做，不需要新的输入或输出设备来查看时钟信号。

3. 发明授权

US08166246B2 Chaining multiple smaller store queue entries for more efficient store queue usage 有权
标题翻译：链接多个较小的存储队列条目，以实现更高效的存储队列使用
公开(公告)号：US08166246B2
公开(公告)日：2012-04-24
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译：数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。响应于第一段不等于第二段，第一个条目链接到第二个条目。

4. 发明授权

US06834356B1 Functional clock generation controlled by JTAG extensions 失效
标题翻译：功能时钟产生由JTAG扩展控制
公开(公告)号：US06834356B1
公开(公告)日：2004-12-21
申请号：US09504973
申请日：2000-02-15
申请人： William Lloyd McNeil
发明人： William Lloyd McNeil
IPC分类号： G06F104
CPC分类号： G01R31/318552 , G06F1/04 , G06F1/22
摘要： An on-chip clock generation system used the Serial Interface in an on-chip JTAG facility to write bit patterns in a shift register. The bit patterns are applied to control inputs of a clock generation circuit whose clock outputs are varied in accordance with changes to the bit patterns. By using the same facility to provide JTAG and clock functions the output clocks provided by clock generation circuit on the chip can be varied without using additional pins or the output clocks themselves.
摘要翻译：片上时钟产生系统使用片上JTAG工具中的串行接口将位模式写入移位寄存器。位模式被应用于时钟发生电路的控制输入，其时钟输出根据位模式的改变而变化。通过使用相同的功能来提供JTAG和时钟功能，芯片上时钟产生电路提供的输出时钟可以在不使用额外引脚或输出时钟本身的情况下进行变化。

5. 发明授权

US5790714A System and method for scaling video 失效
标题翻译：用于缩放视频的系统和方法
公开(公告)号：US5790714A
公开(公告)日：1998-08-04
申请号：US332961
申请日：1994-11-01
申请人： William Lloyd McNeil , David Carl Frank
发明人： William Lloyd McNeil , David Carl Frank
IPC分类号： H04N1/393 , G06T3/40 , G06K9/32
CPC分类号： G06T3/4007
摘要： Scaling of video is performed using area weighted averaging of input pixels to calculate coefficients to multiply with luminescence and crominence of input pixels. Such coefficients are produced for both the vertical and horizontal scaling directions of the input video stream. When scaling down or scaling up, scaling is first performed in the vertical direction to produce partially scaled pixels, which are then utilized for scaling in the horizontal direction. When scaling up, a pre-interpolation or pre-replication process is utilized to double the inputted pixel grid which doubled pixel grid is then utilized to scale down to the desired pixel grid size, which is greater than the originally inputted pixel grid size.
摘要翻译：使用输入像素的区域加权平均来执行视频的缩放，以计算与输入像素的发光和色度相乘的系数。对于输入视频流的垂直和水平缩放方向都产生这样的系数。当缩小或缩小时，首先在垂直方向上执行缩放以产生部分缩放的像素，然后将其用于水平方向上的缩放。当放大时，使用预插入或预复制过程将输入的像素网格加倍，然后将双倍像素网格用于缩小到大于原始输入的像素网格尺寸的期望像素网格大小。

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