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1. 发明授权

US09443114B1 Auto-logging of read/write commands in a storage network 有权
标题翻译：在存储网络中自动记录读/写命令
公开(公告)号：US09443114B1
公开(公告)日：2016-09-13
申请号：US12031658
申请日：2008-02-14
申请人： William C. Wong , Kha Nguyen , Huy Tu Nguyen , William W. Dennin, III , Roger Baldwin
发明人： William C. Wong , Kha Nguyen , Huy Tu Nguyen , William W. Dennin, III , Roger Baldwin
IPC分类号： G06F21/80 , G06F11/34
CPC分类号： G06F21/805 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G06F11/3476
摘要： A system and method for verifying an identifier of a command. The method includes receiving an incoming command and sending a first alert to auto-logging hardware, wherein the auto-logging hardware sends a fetch instruction in response to receiving the first alert; retrieving an identifier of the incoming command in response to the fetch instruction and sending a second alert to the auto-logging hardware, wherein the auto-logging hardware sends a search instruction in response to receiving the second alert; and searching for the identifier of the incoming command in a table in response to the search instruction, the table storing identifiers previously assigned to other commands, wherein the incoming command is logged into the search table and marked as a searched command after the search for the first identifier in the table has completed successfully.
摘要翻译：一种用于验证命令的标识符的系统和方法。该方法包括接收输入命令并向自动登录硬件发送第一警报，其中自动记录硬件响应于接收到第一警报而发送取指令; 响应于所述获取指令检索所述输入命令的标识符并向所述自动登录硬件发送第二警报，其中所述自动记录硬件响应于接收到所述第二警报而发送搜索指令; 并且响应于搜索指令在表中搜索输入命令的标识符，所述表存储器先前分配给其他命令，其中，输入命令被登录到搜索表中，并且在搜索之后被标记为搜索命令表中的第一个标识符已成功完成。

2. 发明授权

US07949838B1 System and method for managing a memory storage device 有权
标题翻译：用于管理存储器件的系统和方法
公开(公告)号：US07949838B1
公开(公告)日：2011-05-24
申请号：US12611131
申请日：2009-11-03
申请人： William C. Wong , Kha Nguyen , Huy Tu Nguyen
发明人： William C. Wong , Kha Nguyen , Huy Tu Nguyen
IPC分类号： G06F12/00
CPC分类号： G11B20/10527 , G11B20/18 , G11B2020/10638 , G11B2020/1843 , G11B2220/2516 , G11B2220/2562
摘要： A memory management system includes a memory controller module configured to receive a frame of data. The frame of data includes a plurality of data words that generate boundary indicators based on at least one of a start of the frame and an end of the frame. The plurality of data words inserts the boundary indicators into the frame of data. The memory is configured to store the frame of data, including the data words and the boundary indicators, during transmission of the frame of data between a host and a storage device.
摘要翻译：存储器管理系统包括被配置为接收数据帧的存储器控制器模块。数据帧包括基于帧的开始和帧的结束中的至少一个生成边界指示符的多个数据字。多个数据字将边界指示符插入到数据帧中。存储器被配置为在主机和存储设备之间的数据帧传输期间存储数据帧，包括数据字和边界指示符。

3. 发明授权

US5579016A Phased array multiple area nulling antenna architecture 失效
标题翻译：相控阵多区域归零天线架构
公开(公告)号：US5579016A
公开(公告)日：1996-11-26
申请号：US531262
申请日：1995-09-20
申请人： James L. Wolcott , William C. Wong , Kenneth E. Westall
发明人： James L. Wolcott , William C. Wong , Kenneth E. Westall
IPC分类号： G01S3/16 , G01S3/28 , H01Q3/22 , H01Q3/26 , H01Q3/24
CPC分类号： H01Q3/22 , H01Q3/2605
摘要： An adaptive nulling communication system for nulling undesired signals from communication signals in multiple separate and distinct coverage areas is disclosed. The adaptive nulling communication system includes a phased array antenna having multiple receiving elements to form a single aperture for receiving multiple signals. A first set of beam forming networks coupled to the phased array antenna forms the multiple separate and distinct coverage areas. A distribution network coupled to the first set of beam forming networks distributes the signals received from these coverage areas. A nulling processor having a second beam forming network coupled to the distribution network weights and adjusts the second beam forming network in response to the undesired signals to null these undesired signals from the communication signals.
摘要翻译：公开了一种用于在多个独立且不同的覆盖区域中对来自通信信号的不想要的信号进行归零的自适应归零通信系统。自适应归零通信系统包括具有多个接收元件以形成用于接收多个信号的单个孔径的相控阵天线。耦合到相控阵天线的第一组波束形成网络形成多个分开且不同的覆盖区域。耦合到第一组波束形成网络的分配网络分配从这些覆盖区域接收的信号。具有耦合到分配网络的第二波束形成网络的归零处理器加权并响应于不期望的信号调整第二波束形成网络，以从通信信号中将这些不期望的信号置零。

4. 发明授权

US08412895B1 Hard disk controller which coordinates transmission of buffered data with a host 有权
标题翻译：与主机协调传输缓冲数据的硬盘控制器
公开(公告)号：US08412895B1
公开(公告)日：2013-04-02
申请号：US13401179
申请日：2012-02-21
申请人： Huy Tu Nguyen , William C. Wong , Kha Nguyen
发明人： Huy Tu Nguyen , William C. Wong , Kha Nguyen
IPC分类号： G06F12/00
CPC分类号： G06F5/065 , G06F3/061 , G06F3/0659 , G06F3/0674
摘要： The transmission of buffered data is coordinated between a storage medium and a host in response to a request from the host. One or more blocks of data are transferred from the storage medium to a buffer memory. One or more frames of data are transmitted from the buffer memory to the host, wherein the number of blocks ending in the frame is recorded in a blocks/frame register, and possibly also in a block count accumulator register. Buffer release pulses for releasing buffer space in memory are sent to the buffer memory, based on the number of blocks in the blocks/frame register, or the number of blocks accumulated in the block count accumulator register when a signal is received from the host. A pointer which points to the last block of data successfully transferred is updated in accordance with the buffer release pulses.
摘要翻译：响应于来自主机的请求，缓冲数据的传输在存储介质和主机之间协调。一个或多个数据块从存储介质传送到缓冲存储器。一个或多个数据帧从缓冲存储器发送到主机，其中以帧结束的块的数量被记录在块/帧寄存器中，并且还可能被记录在块计数累加器寄存器中。基于块/帧寄存器中的块数或从主机接收到信号时累积在块计数累加器寄存器中的块的数量，将用于释放存储器中的缓冲器空间的缓冲器释放脉冲发送到缓冲存储器。根据缓冲器释放脉冲更新指向成功传送的最后数据块的指针。

5. 发明授权

US08156415B1 Method and system for command queuing in disk drives 有权
标题翻译：磁盘驱动器中命令排队的方法和系统
公开(公告)号：US08156415B1
公开(公告)日：2012-04-10
申请号：US12323267
申请日：2008-11-25
申请人： Huy Tu Nguyen , William C. Wong , Kha Nguyen , Yehua Yang
发明人： Huy Tu Nguyen , William C. Wong , Kha Nguyen , Yehua Yang
IPC分类号： G06F11/08 , G06F13/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0671 , G06F11/1004 , G06F2213/0038
摘要： A method and system for command queuing in disk drives may improve performance by queuing multiple commands and sequentially executing them automatically without firmware intervention. The method may use a number of queues, e.g., a staging queue for commands to be executed, an execution queue for commands currently being executed, and a holding queue for commands which have been executed but have not received a status report from a host. With the pipelined nature of queued commands, when data requested by one command are being sent to the host, the queue logic may already be fetching data for the next command. If an error occurs in the transmission, commands in the queues may backtrack and restart from the point where data were last known to have been successfully sent to the host.
摘要翻译：用于在磁盘驱动器中进行命令排队的方法和系统可以通过排队多个命令并在没有固件干预的情况下自动执行它们来提高性能。该方法可以使用多个队列，例如用于执行命令的分段队列，用于当前正在执行的命令的执行队列，以及用于已被执行但尚未从主机接收到状态报告的命令的保持队列。随着排队命令的流水线性质，当一个命令请求的数据被发送到主机时，队列逻辑可能已经为下一个命令获取数据。如果传输中发生错误，则队列中的命令可能会从最后被称为已经成功发送到主机的位置回溯并重新启动。

6. 发明授权

US5627858A Multi-channel autobauding circuit 失效
标题翻译：多通道自动波特率电路
公开(公告)号：US5627858A
公开(公告)日：1997-05-06
申请号：US480546
申请日：1995-06-07
申请人： Simon C. Mak , William C. Wong
发明人： Simon C. Mak , William C. Wong
IPC分类号： H04L25/02 , H04B3/46
CPC分类号： H04L25/0262
摘要： A system and method for data transfer. The system determines the baud rate of a plurality channels carrying of asynchronous data streams by measuring a time period T between the beginning of a start bit and the transition to a logic high at the beginning of each odd-ASCII character. The system assesses baud rates over a continuous variable range. The system loops back data to its source to provide an echo while determining the baud rate.
摘要翻译：一种用于数据传输的系统和方法。该系统通过测量在每个奇数ASCII字符的开始处开始位开始和转换到逻辑高的时间段T来确定携带异步数据流的多个通道的波特率。系统评估连续可变范围内的波特率。系统将数据循环回源，以确定波特率时提供回声。

7. 发明授权

US5410318A Simplified wide-band autotrack traveling wave coupler 失效
标题翻译：简化宽带自动跟踪行波耦合器
公开(公告)号：US5410318A
公开(公告)日：1995-04-25
申请号：US218775
申请日：1994-03-25
申请人： William C. Wong , Youn H. Choung , Ming-Jong Shiau , Chun-Hong H. Chen
发明人： William C. Wong , Youn H. Choung , Ming-Jong Shiau , Chun-Hong H. Chen
IPC分类号： H01P1/16 , H01P5/18 , H01Q1/12 , H01Q3/06 , H01Q3/00
CPC分类号： H01Q1/1257 , H01P1/16 , H01P5/182 , H01Q3/06
摘要： In accordance with the present invention, a traveling wave coupler generates tracking signals from a circularly polarized microwave signal and includes a waveguide manifold for exciting circular TM.sub.01 and TM.sub.11 modes of said circularly polarized microwave signal. The waveguide manifold includes an input port, a propagation length, and an output port. A coupling arm waveguide includes an auxiliary input port and an auxiliary output port and is aligned and connected to the waveguide manifold along a portion of the propagation length. A coupler located between the waveguide manifold and the coupling arm transforms microwave energy of a TM.sub.01 mode of the circularly polarized microwave signal into a rectangular TE.sub.10 mode in the coupling arm waveguide. The coupling arm waveguide and the coupler generate a difference signal, used to generate the tracking signals, at the auxiliary output port related to the coupled TE.sub.10 mode.
摘要翻译：根据本发明，行波耦合器从圆偏振微波信号产生跟踪信号，并且包括用于激励所述圆偏振微波信号的圆形TM01和TM11模式的波导歧管。波导歧管包括输入端口，传播长度和输出端口。耦合臂波导包括辅助输入端口和辅助输出端口，并且沿着传播长度的一部分对准并连接到波导歧管。位于波导歧管和耦合臂之间的耦合器将耦合臂波导中的圆偏振微波信号的TM01模式的微波能量转换为矩形TE10模式。耦合臂波导和耦合器在与耦合的TE10模式相关的辅助输出端口处产生用于产生跟踪信号的差分信号。

8. 发明授权

US07953907B1 Concurrent input/output control and integrated error management in FIFO 有权
标题翻译：并行输入/输出控制和FIFO中的集成错误管理
公开(公告)号：US07953907B1
公开(公告)日：2011-05-31
申请号：US11840059
申请日：2007-08-16
申请人： Huy Tu Nguyen , William C. Wong , Kha Nguyen
发明人： Huy Tu Nguyen , William C. Wong , Kha Nguyen
IPC分类号： G06F3/00 , G06F11/00
CPC分类号： G06F11/0793
摘要： A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.
摘要翻译： FIFO存储器具有集成的错误管理功能，可以根据当前的输入和输出操作状态以及内部条件（如缓冲存储器状态）对不同的错误做出反应。 FIFO存储器根据状态完成或中止当前操作，并在错误处理后将FIFO存储器留在已知状态。因此，发送到主机的数据避免了数据间隙或数据重叠，因为在将错误报告给控制器之前，FIFO存储器将操作置于已知状态。

9. 发明授权

US08271701B1 Concurrent input/output control and integrated error management in FIFO 有权
标题翻译：并行输入/输出控制和FIFO中的集成错误管理
公开(公告)号：US08271701B1
公开(公告)日：2012-09-18
申请号：US13117974
申请日：2011-05-27
申请人： Huy Tu Nguyen , William C. Wong , Kha Nguyen
发明人： Huy Tu Nguyen , William C. Wong , Kha Nguyen
IPC分类号： G06F3/00
CPC分类号： G06F11/0793
摘要： A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.
摘要翻译： FIFO存储器具有集成的错误管理功能，可以根据当前的输入和输出操作状态以及内部条件（如缓冲存储器状态）对不同的错误做出反应。 FIFO存储器根据状态完成或中止当前操作，并在错误处理后将FIFO存储器留在已知状态。因此，发送到主机的数据避免了数据间隙或数据重叠，因为在将错误报告给控制器之前，FIFO存储器将操作置于已知状态。

10. 发明授权

US08032674B2 System and method for controlling buffer memory overflow and underflow conditions in storage controllers 有权
标题翻译：用于控制存储控制器中缓冲存储器溢出和下溢条件的系统和方法
公开(公告)号：US08032674B2
公开(公告)日：2011-10-04
申请号：US10894208
申请日：2004-07-19
申请人： Kha Nguyen , William C. Wong , Mouluan Jang , Jane X. Wang
发明人： Kha Nguyen , William C. Wong , Mouluan Jang , Jane X. Wang
IPC分类号： G06F5/00 , G06F11/00
CPC分类号： G06F3/0605 , G06F3/0656 , G06F3/0676
摘要： A method for maintaining flow control in a buffer memory coupled to a storage controller is provided. The storage controller includes, first and second counters that are used to monitor when data is read from a buffer memory and when data is transferred from the buffer memory to the host. The method includes, incrementing first and second counter values when data is placed in the buffer memory; decrementing a first counter value when data is read from the buffer memory; and decrementing the second counter value when data is sent to a host. The method further includes, pausing a first channel logic between a transport module and a storage disk when there is no data in the buffer memory; and pausing a second channel logic between a disk and the buffer if there is no space in the buffer memory.
摘要翻译：提供了一种用于维持耦合到存储控制器的缓冲存储器中的流量控制的方法。存储控制器包括用于监视从缓冲存储器读取数据以及数据从缓冲存储器传送到主机的第一和第二计数器。该方法包括：当数据放置在缓冲存储器中时，递增第一和第二计数器值; 当从缓冲存储器读取数据时递减第一计数器值; 并且当数据被发送到主机时递减第二计数器值。该方法还包括：当缓冲存储器中没有数据时，暂停传输模块和存储盘之间的第一通道逻辑; 并且如果缓冲存储器中没有空间，则在盘和缓冲器之间暂停第二通道逻辑。

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