专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5163149A Combining switch for reducing accesses to memory and for synchronizing parallel processes 失效
标题翻译：组合开关，用于减少对存储器的访问和同步并行过程
公开(公告)号：US5163149A
公开(公告)日：1992-11-10
申请号：US266424
申请日：1988-11-02
申请人： William C. Brantley, Jr. , Harold S. Stone
发明人： William C. Brantley, Jr. , Harold S. Stone
IPC分类号： G06F15/16 , G06F9/52 , G06F15/173 , G06F15/177
CPC分类号： G06F15/17337
摘要： A combining switch that reduces memory accesses, synchronizes parallel processors and is easy to implement, is achieved by configuring a plurality of parallel processing nodes in a ring arrangement and by implementing a synchronizing instruction for the switch that facilitates, rather than inhibits, parallel processing. According to the preferred embodiment of the invention the ring is a token ring and the synchronizing instruction is a Fetch-and-Add instruction.

2. 发明授权

US4885680A Method and apparatus for efficiently handling temporarily cacheable data 失效
标题翻译：用于有效地处理临时可缓存数据的方法和装置
公开(公告)号：US4885680A
公开(公告)日：1989-12-05
申请号：US890428
申请日：1986-07-25
申请人： John H. Anthony , William C. Brantley, Jr. , Kevin P. McAuliffe , Vern A. Norton , Gregory F. Pfister
发明人： John H. Anthony , William C. Brantley, Jr. , Kevin P. McAuliffe , Vern A. Norton , Gregory F. Pfister
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1045 , G06F12/0837
摘要： A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data. When an "invalidate marked data" instruction is received, the cache controls sweep through the entire cache directory and invalidate any cache line which has the "marked data bit" set in a single pass. An extension of the invention involves using a multi-bit field rather than a single bit to provide a more versatile control of the temporary cacheability of data.
摘要翻译：一种用于标记数据的方法和装置，该数据可临时高速缓存以便于所述数据的有效管理。称为标记数据位（MDB）的数据的段和/或页面描述符中的一位由编译器生成，并被包含在存储器地址形式中由处理器从存储器请求数据的请求中，并存储在在与所涉及的特定数据行相关的位置处的缓存目录。该位在地址转换之后（在实际高速缓存的情况下）与相关联的实际地址一起被传递到高速缓存。当缓存控件加载目录中的数据的地址时，它也将标记的数据位（MDB）存储在具有地址的目录中。当临时可缓存数据的可缓存性从可高速缓存改变为不可缓存时，将发出单个指令以使缓存无效所有标记的数据。当接收到“无效的标记数据”指令时，高速缓存控制扫描整个高速缓存目录，并使在一次通过中设置的“标记数据位”的任何高速缓存行无效。本发明的扩展涉及使用多比特字段而不是单个比特来提供数据的临时高速缓存的更通用的控制。

3. 发明授权

US5125096A System for implementing to a packet switch protocol for a multinode data communications network utilizing separate data and control paths 失效
标题翻译：用于实现分组数据通信网络的分组交换协议的系统，利用单独的数据和控制码
公开(公告)号：US5125096A
公开(公告)日：1992-06-23
申请号：US264419
申请日：1988-10-31
申请人： William C. Brantley, Jr. , Wayne S. Groh , Rory D. Jackson , Vern A. Norton
发明人： William C. Brantley, Jr. , Wayne S. Groh , Rory D. Jackson , Vern A. Norton
IPC分类号： H04L13/08 , H04L12/56 , H04L29/06
CPC分类号： H04L12/56 , H04L29/06
摘要： Packet switch protocol and circuitry for implementing it are disclosed. According to this protocol, a message transmitter of a first node in the network may send data through a data transmission link at a predetermined rate until it is signalled, via a control signal generated by a message receiver in a second node, to suspend its transmissions. The message transmitter may also be signalled to resume transmitting data. The message receiver includes a buffer memory in which messages are temporarily stored if their selected path is blocked as they pass through the network. When the amount of available space in the buffer is less than a preprogrammed threshold value, the message receiver generates the control signal to suspend message transmission. This threshold value leaves sufficient space in the buffer to store any data which may be in the pipeline between the transmitter and the receiver. When the amount of available space rises above this threshold, the message receiver indicates to the transmitter to resume transmission. A message spanning an interface during transmission may be suspended without losing spatial contiguousness. The message transmitter also transmits a signal which marks the last portion of a message. This signal is stored in the buffer with the message data and is used to delimit messages in the buffer, allowing multiple messages to be stored in one buffer without extra delimiting values.

4. 发明授权

US4980822A Multiprocessing system having nodes containing a processor and an associated memory module with dynamically allocated local/global storage in the memory modules 失效
标题翻译：具有包含处理器和相关联的存储器模块的节点的多处理系统具有在存储器模块中动态分配的本地/全局存储器
公开(公告)号：US4980822A
公开(公告)日：1990-12-25
申请号：US168721
申请日：1988-03-16
申请人： William C. Brantley, Jr. , Kevin P. McAuliffe , Vern A. Norton , Gregory F. Pfister , Joseph Weiss
发明人： William C. Brantley, Jr. , Kevin P. McAuliffe , Vern A. Norton , Gregory F. Pfister , Joseph Weiss
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08 , G06F15/17
CPC分类号： G06F12/0292 , G06F12/0692
摘要： A multiprocessing system is presented having a plurality of processing nodes interconnected together by a communication network, each processing node including a processor, responsive to user software running on the system, and an associated memory module, and capable under user control of dynamically partitioning each memory module into a global storage efficiently accessible by a number of processors connected to the network, and local storage efficiently accessible by its associated processor.
摘要翻译：呈现多处理系统，其具有通过通信网络互连在一起的多个处理节点，每个处理节点包括响应于在系统上运行的用户软件的处理器和相关联的存储器模块，并且能够在用户控制下动态地划分每个存储器模块进入由连接到网络的多个处理器有效访问的全局存储器，以及由其相关联的处理器有效访问的本地存储器。

5. 发明授权

US4754394A Multiprocessing system having dynamically allocated local/global storage and including interleaving transformation circuit for transforming real addresses to corresponding absolute address of the storage 失效
标题翻译：多处理系统具有动态分配的本地/全局存储，并且包括交织变换电路，用于将实际地址转换为相应的存储绝对地址
公开(公告)号：US4754394A
公开(公告)日：1988-06-28
申请号：US664131
申请日：1984-10-24
申请人： William C. Brantley, Jr. , Kevin P. McAuliffe , Vern A. Norton , Gregory F. Pfister , Joseph Weiss
发明人： William C. Brantley, Jr. , Kevin P. McAuliffe , Vern A. Norton , Gregory F. Pfister , Joseph Weiss
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08 , G06F15/17 , G06F15/16 , G06F12/10
CPC分类号： G06F12/0292 , G06F12/0692
摘要： A multiprocessing system is presented for dynamically partitioning a storage module into a global storage efficiently accessible by a number of processors connected to a network, and local storage efficiently accessible by individual processors, including the interleaving of storage references output by a processor, under the control of that processor, and dynamically directing the storage references to first or second portions of the storage module.
摘要翻译：提出了一种多处理系统，用于将存储模块动态地划分成由连接到网络的多个处理器可有效访问的全局存储器，以及由各个处理器有效访问的本地存储器，包括在控制下由处理器输出的存储引用的交错并且将存储引用动态地引导到存储模块的第一或第二部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式