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1. 发明授权

US08665054B2 Semiconductor component with coreless transformer 有权
标题翻译：具有无芯变压器的半导体元件
公开(公告)号：US08665054B2
公开(公告)日：2014-03-04
申请号：US13452075
申请日：2012-04-20
申请人： Matthias Stecher , Markus Menath , Andreas Zankl , Werner Robl
发明人： Matthias Stecher , Markus Menath , Andreas Zankl , Werner Robl
IPC分类号： H01F5/00 , H01L27/08
CPC分类号： H01L28/10 , H01F27/2804 , H01F2017/0086 , H01L23/5225 , H01L23/5227 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.
摘要翻译：半导体部件集成了无芯变压器与第一连接触点，第二连接触点，导电螺旋第一线圈，导电第一环和导电第二环。导电螺旋第一线圈电连接在第一连接触点和第二连接触点之间。导电的第一环围绕第一线圈和第一连接触点和第二连接触点中的一个或两个。导电的第二环被布置在第一线圈和第一环之间，电连接到第一线圈，并且包围第一线圈以及第一连接触点和第二连接触点中的一个或两者。

2. 发明授权

US08330274B2 Semiconductor structure and method for making same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08330274B2
公开(公告)日：2012-12-11
申请号：US12893009
申请日：2010-09-29
申请人： Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
发明人： Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76879 , H01L23/49816 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L24/03 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01042 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/0106 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/00
摘要： One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
摘要翻译：一个或多个实施例涉及一种形成半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成种子层; 在种子层上形成抑制层; 去除所述抑制剂层的一部分以暴露所述种子层的一部分; 并且在曝光的种子层上选择性地沉积填充层。

3. 发明授权

US08148257B1 Semiconductor structure and method for making same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08148257B1
公开(公告)日：2012-04-03
申请号：US12894190
申请日：2010-09-30
申请人： Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
发明人： Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/469
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L21/76885 , H01L23/53223 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
摘要翻译：一个或多个实施例涉及一种形成电子设备的方法，包括：提供工件; 在工件上形成第一阻挡层; 在所述第一阻挡层上形成中间导电层; 在所述中间导电层上形成第二阻挡层; 在所述第二阻挡层上形成种子层; 去除种子层的一部分以留下种子层的剩余部分并暴露第二阻挡层的一部分; 并在种子层的剩余部分上电镀填充层。

4. 发明申请

US20110101532A1 DEVICE FABRICATED USING AN ELECTROPLATING PROCESS 有权
标题翻译：使用电镀工艺制作的器件
公开(公告)号：US20110101532A1
公开(公告)日：2011-05-05
申请号：US12611609
申请日：2009-11-03
申请人： Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
发明人： Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
IPC分类号： H01L23/48 , H05K1/00 , C25D5/00 , C25D5/34
CPC分类号： H01L23/5389 , H01L21/486 , H01L21/76873 , H01L21/76879 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/82 , H01L24/97 , H01L2221/1089 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1461 , H01L2924/181 , H01L2224/82 , H01L2924/00
摘要： A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
摘要翻译：一种用于制造器件的方法包括提供包括至少一个接触的衬底并在衬底上施加电介质层。该方法包括在电介质层上施加第一种子层，在种子层上施加惰性层，以及构造惰性层，第一籽晶层和电介质层以暴露至少一部分接触。该方法包括在结构化介电层和触点的暴露部分上施加第二种子层，使得第二籽晶层与结构化的第一籽晶层电接触。该方法包括在第二种子层上电镀金属。

5. 发明申请

US20100188905A1 Spin Device 有权
标题翻译：旋转装置
公开(公告)号：US20100188905A1
公开(公告)日：2010-07-29
申请号：US12358721
申请日：2009-01-23
申请人： Gerhard Poeppel , Hans-Joerg Timme , Werner Robl
发明人： Gerhard Poeppel , Hans-Joerg Timme , Werner Robl
IPC分类号： G11C15/02 , H01L29/66
CPC分类号： H01L29/66984 , B82Y25/00 , H01F10/3254
摘要： According to an embodiment of the present invention, a spin device includes an intermediate semiconductor region arranged between a first terminal and a second terminal, wherein the first terminal is adapted to provide a current having a first degree of spin polarization to the intermediate semiconductor region, and wherein the second terminal is adapted to output the current having a second degree of spin polarization. The spin device further includes a spin selective scattering structure abutting the intermediate semiconductor region, the spin selective scattering structure being adapted such that the first degree of spin polarization is altered to be the second degree, wherein the spin selective scattering structure comprises a control electrode being electrically insulated from the intermediate semiconductor region, and wherein the control electrode is adapted to apply an electrical field perpendicular to a direction of the current through the intermediate semiconductor region to control a magnitude of the current.
摘要翻译：根据本发明的实施例，自旋装置包括布置在第一端子和第二端子之间的中间半导体区域，其中第一端子适于向中间半导体区域提供具有第一自旋极化度的电流，并且其中所述第二端子适于输出具有第二自旋极化度的电流。自旋装置还包括邻接中间半导体区域的自旋选择性散射结构，自旋选择性散射结构适于使第一自旋极化程度改变为第二程度，其中自旋选择性散射结构包括控制电极与中间半导体区域电绝缘，并且其中控制电极适于施加垂直于通过中间半导体区域的电流的方向的电场以控制电流的大小。

6. 发明申请

US20080257744A1 METHOD OF MAKING AN INTEGRATED CIRCUIT INCLUDING ELECTRODEPOSITION OF ALUMINIUM 审中-公开
标题翻译：制造包含铝电沉积的集成电路的方法
公开(公告)号：US20080257744A1
公开(公告)日：2008-10-23
申请号：US11737530
申请日：2007-04-19
申请人： Johannes Lodermeyer , Edmund Riedl , Werner Robl
发明人： Johannes Lodermeyer , Edmund Riedl , Werner Robl
IPC分类号： C25D3/56
CPC分类号： C25D3/44 , C25D17/002 , C25D17/004 , C25D21/11
摘要： A method of making an integrated circuit including composition of matter for electrodepositing of aluminium is disclosed. One embodiment includes a bath having a solution of selected aluminium salts in a substantially anhydrous organic solvent, to uses of certain aluminium salts for electrodepositing and to processes for electrodepositing aluminium.
摘要翻译：公开了一种制造集成电路的方法，该集成电路包括用于电沉积铝的物质的组成。一个实施方案包括具有选定的铝盐在基本上无水的有机溶剂中的溶液的浴，使用某些铝盐进行电沉积和电沉积铝的方法。

7. 发明授权

US06943114B2 Integration scheme for metal gap fill, with fixed abrasive CMP 有权
标题翻译：金属间隙填充的集成方案，固定磨料CMP
公开(公告)号：US06943114B2
公开(公告)日：2005-09-13
申请号：US10084194
申请日：2002-02-28
申请人： Peter Wrschka , Werner Robl , Thomas Goebel
发明人： Peter Wrschka , Werner Robl , Thomas Goebel
IPC分类号： H01L21/3105 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31053 , Y10S438/959
摘要： In a method of planarizing a semiconductor wafer, the improvement comprising polishing above metal interconnect lines to uniformly polish the topography of the wafer to a predetermined endpoint on the wafer sufficiently close above the metal interconnect lines, yet far enough away from the lines to prevent damage to the lines, comprising:a) filling gaps between metal interconnect lines of an inter metal dielectric in a wafer being formed, by depositing HDP fill on top of the metal interconnects, between the metal interconnects, and on the surface of a dielectric layer between the metal interconnects to create an HDP overfill;b) contacting the surface of HDP overfill of the processed semiconductor wafer from step a) with a fixed abrasive polishing pad; andc) relatively moving the wafer and the fixed abrasive polishing pad to affect a polishing rate sufficient to reach a predetermined endpoint and uniformly planar surface on the wafer sufficiently close above the metal interconnect lines and yet far enough away from the lines to prevent damage to the lines.
摘要翻译：在平坦化半导体晶片的方法中，改进包括在金属互连线上方抛光，以将晶片的形貌均匀地抛光到晶片上的预定端点上，该晶圆足够靠近金属互连线上方，远离线路远离线以防止损坏包括：a）通过在金属互连件的顶部，金属互连件之间以及电介质层的表面上沉积HDP填充物，填充在形成的晶片之间的金属互连线之间的间隙，金属互连以产生HDP溢出; b）使来自步骤a）的经处理的半导体晶片的HDP的填充表面与固定的研磨抛光垫接触; 以及c）相对移动所述晶片和所述固定研磨抛光垫以影响足以达到所述晶片上的预定端点和所述晶片上的均匀平坦表面的抛光速率，所述平坦表面足够靠近所述金属互连线，并且远离所述线远离所述线，以防止损坏线条。

8. 发明申请

US20130278372A1 Semiconductor Component with Coreless Transformer 有权
标题翻译：无芯变压器半导体元件
公开(公告)号：US20130278372A1
公开(公告)日：2013-10-24
申请号：US13452075
申请日：2012-04-20
申请人： Matthias Stecher , Markus Menath , Andreas Zankl , Werner Robl
发明人： Matthias Stecher , Markus Menath , Andreas Zankl , Werner Robl
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01F27/2804 , H01F2017/0086 , H01L23/5225 , H01L23/5227 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.
摘要翻译：半导体部件集成了无芯变压器与第一连接触点，第二连接触点，导电螺旋第一线圈，导电第一环和导电第二环。导电螺旋第一线圈电连接在第一连接触点和第二连接触点之间。导电的第一环围绕第一线圈和第一连接触点和第二连接触点中的一个或两个。导电的第二环被布置在第一线圈和第一环之间，电连接到第一线圈，并且包围第一线圈以及第一连接触点和第二连接触点中的一个或两者。

9. 发明申请

US20130147047A1 Integrated Circuit and Method of Forming an Integrated Circuit 有权
标题翻译：集成电路和形成集成电路的方法
公开(公告)号：US20130147047A1
公开(公告)日：2013-06-13
申请号：US13315642
申请日：2011-12-09
申请人： Thomas Detzel , Johann Gross , Robert Illing , Maximilian Krug , Sven Gustav Lanzerstorfer , Michael Nelhiebel , Werner Robl , Michael Rogalli , Stefan Woehlert
发明人： Thomas Detzel , Johann Gross , Robert Illing , Maximilian Krug , Sven Gustav Lanzerstorfer , Michael Nelhiebel , Werner Robl , Michael Rogalli , Stefan Woehlert
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L23/3735 , H01L21/2885 , H01L21/4882 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.
摘要翻译：集成电路包括在基底元件上的基底元件和铜元件，铜元件具有至少5μm的厚度，并且平均晶粒尺寸与厚度之比小于0.7。

10. 发明授权

US06734097B2 Liner with poor step coverage to improve contact resistance in W contacts 有权
标题翻译：衬垫差步幅覆盖，以提高W触点的接触电阻
公开(公告)号：US06734097B2
公开(公告)日：2004-05-11
申请号：US09965094
申请日：2001-09-28
申请人： Roy C. Iggulden , Padraic Shafer , Werner Robl , Kwong Hon Wong
发明人： Roy C. Iggulden , Padraic Shafer , Werner Robl , Kwong Hon Wong
IPC分类号： H01L214763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.
摘要翻译：一种用衬垫填充镶嵌结构的方法，其特征在于改进的阻力和阻力扩展以及足够的粘合性，其包括：由衬垫涂覆的给定镶嵌结构，其有目的地为上述结构提供差的步骤覆盖，随后进行CVD W沉积，其次是金属隔离技术。

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