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1. 发明申请

US20090100313A1 METHODS AND APPARATUSES OF MATHEMATICAL PROCESSING 审中-公开
标题翻译：数学处理的方法与设备
公开(公告)号：US20090100313A1
公开(公告)日：2009-04-16
申请号：US12250830
申请日：2008-10-14
申请人： Warren J. GROSS , Shie MANNOR , Saeed SHARIFI TEHRANI
发明人： Warren J. GROSS , Shie MANNOR , Saeed SHARIFI TEHRANI
IPC分类号： H03M13/05 , G06F7/38 , G06F7/58 , G06F11/10
CPC分类号： G06F7/58
摘要： Disclosed is a pipelined iterative process and system. Data is received at an input port and is processed in a symbolwise fashion. Processing of each symbol is performed other than relying on completing the processing of an immediately preceding symbol such that operation of the system or process is independent of an order of the input symbols.
摘要翻译：公开了一种流水线迭代过程和系统。在输入端口接收数据，并以符号方式进行处理。执行每个符号的处理，而不是依靠完成紧接在前的符号的处理，使得系统或过程的操作与输入符号的顺序无关。

2. 发明申请

US20080256343A1 Convergence determination and scaling factor estimation based on sensed switching activity or measured power consumption 审中-公开
标题翻译：基于感测的开关活动或测量的功耗的收敛确定和缩放因子估计
公开(公告)号：US20080256343A1
公开(公告)日：2008-10-16
申请号：US12081155
申请日：2008-04-11
申请人： Warren J. Gross , Shie Mannor
发明人： Warren J. Gross , Shie Mannor
IPC分类号： H01R13/60 , H03K19/003
CPC分类号： G05B19/045
摘要： A method and system for determining convergence of iterative processes and estimating a scaling factor in decoding processes based on switching activity of the logic circuitry are provided. During execution of an iterative process using logic circuitry comprising logic gates switching activity of a plurality of the logic gates is sensed to determine switching data indicative of a total switching activity of the plurality of the logic gates. The iterative process is iterated using the logic circuitry until convergence is indicated by the switching data. Similarly, a scaling factor for use in decoding processes is determined based on the switching data.
摘要翻译：提供了一种用于确定迭代过程的收敛并基于逻辑电路的切换活动来估计解码过程中的缩放因子的方法和系统。在使用包括逻辑门的逻辑电路的迭代处理的执行期间，检测多个逻辑门的切换活动，以确定指示多个逻辑门的总切换活动的切换数据。使用逻辑电路迭代迭代过程，直到收敛由切换数据指示。类似地，基于切换数据确定用于解码处理的缩放因子。

3. 发明授权

US09100153B2 Methods and systems for improving iterative signal processing 有权
标题翻译：改进迭代信号处理的方法和系统
公开(公告)号：US09100153B2
公开(公告)日：2015-08-04
申请号：US13150971
申请日：2011-06-01
申请人： Warren J. Gross , Shie Mannor , Saeed Sharifi Tehrani
发明人： Warren J. Gross , Shie Mannor , Saeed Sharifi Tehrani
IPC分类号： H04L1/00
CPC分类号： H04L1/005
摘要： A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided. A plurality of sub nodes forms a variable node for performing an equality function in an iterative decoding process. Internal memory is interposed between the sub nodes such that the internal memory is connected to an output port of a respective sub node and to an input port of a following sub node, the internal memory for providing a chosen symbol if a respective sub node is in a hold state, and wherein at least two sub nodes share a same internal memory.
摘要翻译：提供了一种用于对从传输信道接收的一组编码样本进行迭代解码的方法。接收表示传输信道的噪声电平的数据信号。然后根据数据信号确定缩放因子，并使用缩放因子对编码的样本进行缩放。然后对经缩放的编码样本进行迭代解码。此外，提供了一种用于初始化边缘存储器的方法。在初始化阶段期间，从逻辑电路的一个节点接收初始化符号并存储在相应的边缘存储器中。当接收到的符号占据边缘存储器的预定部分时，终止初始化阶段。使用存储从边缘存储器中的节点接收的输出符号的逻辑电路来执行迭代处理，并且从边缘存储器检索符号并将其提供为节点的输出符号。还提供了一种用于高度可变节点的架构。多个子节点形成用于在迭代解码处理中执行相等函数的变量节点。内部存储器插入在子节点之间，使得内部存储器连接到相应子节点的输出端口和连接到后续子节点的输入端口，内部存储器用于在各个子节点处于保持状态，并且其中至少两个子节点共享相同的内部存储器。

4. 发明授权

US08108758B2 Stochastic decoding of LDPC codes 有权
标题翻译： LDPC码的随机解码
公开(公告)号：US08108758B2
公开(公告)日：2012-01-31
申请号：US11902410
申请日：2007-09-21
申请人： Warren J. Gross , Shie Mannor
发明人： Warren J. Gross , Shie Mannor
IPC分类号： H03M13/45
CPC分类号： H03M13/1137 , H03M13/1105 , H03M13/1134 , H03M13/1191 , H03M13/1194 , H03M13/19 , H03M13/2957 , H03M13/3723 , H03M13/3753 , H03M13/658
摘要： The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.
摘要翻译：本发明涉及一种用于LDPC码随机解码的解码方法和系统。一组编码样本的每个编码样本首先按照与编码样本集合的噪声电平成比例的缩放因子来缩放。然后将每个经缩放的编码样本转换成相应的概率。对于每个概率，相应的概率消息是通过将每个概率编码为数字比特序列而生成的。然后将每个概率消息提供给用于随机解码的逻辑电路的相应节点。逻辑电路表示LDPC码的奇偶校验矩阵的因子图。使用逻辑电路，每个概率消息被处理以确定信息比特的估计序列。如果等式节点处于保持状态，则从相应的边缘存储器提供所选择的位，当对应的边缘存储器处于除保持状态之外的状态时，通过存储来自等式节点的输出位来更新。

5. 发明申请

US20110293045A1 METHODS AND SYSTEMS FOR IMPROVING ITERATIVE SIGNAL PROCESSING 有权
标题翻译：改进迭代信号处理的方法和系统
公开(公告)号：US20110293045A1
公开(公告)日：2011-12-01
申请号：US13150971
申请日：2011-06-01
申请人： Warren J. Gross , Shie Mannor , Saeed Sharifi Tehrani
发明人： Warren J. Gross , Shie Mannor , Saeed Sharifi Tehrani
IPC分类号： H04L27/06 , H04L27/00
CPC分类号： H04L1/005
摘要： A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided. A plurality of sub nodes forms a variable node for performing an equality function in an iterative decoding process. Internal memory is interposed between the sub nodes such that the internal memory is connected to an output port of a respective sub node and to an input port of a following sub node, the internal memory for providing a chosen symbol if a respective sub node is in a hold state, and wherein at least two sub nodes share a same internal memory.
摘要翻译：提供了一种用于对从传输信道接收的一组编码样本进行迭代解码的方法。接收表示传输信道的噪声电平的数据信号。然后根据数据信号确定缩放因子，并使用缩放因子对编码的样本进行缩放。然后对经缩放的编码样本进行迭代解码。此外，提供了一种用于初始化边缘存储器的方法。在初始化阶段期间，从逻辑电路的一个节点接收初始化符号并存储在相应的边缘存储器中。当接收到的符号占据边缘存储器的预定部分时，终止初始化阶段。使用存储从边缘存储器中的节点接收的输出符号的逻辑电路来执行迭代处理，并且从边缘存储器检索符号并将其提供为节点的输出符号。还提供了一种用于高度可变节点的架构。多个子节点形成用于在迭代解码处理中执行相等函数的变量节点。内部存储器插入在子节点之间，使得内部存储器连接到相应子节点的输出端口和连接到后续子节点的输入端口，内部存储器用于在各个子节点处于保持状态，并且其中至少两个子节点共享相同的内部存储器。

6. 发明申请

US20100017676A1 DECODING OF LINEAR CODES WITH PARITY CHECK MATRIX 有权
标题翻译：用奇偶校验矩阵解码线性代码
公开(公告)号：US20100017676A1
公开(公告)日：2010-01-21
申请号：US12503607
申请日：2009-07-15
申请人： Warren J. GROSS , Shie MANNOR , Gabi SARKIS
发明人： Warren J. GROSS , Shie MANNOR , Gabi SARKIS
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1171 , H04L1/0057
摘要： A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code. Using the logic circuitry each probability message is passed through the factor graph by performing for each received symbol at the variable nodes the equality function, at the permutation nodes one of multiplication and division, and at the parity check nodes the parity check function, wherein each of the variable nodes provides an output symbol in dependence upon each received symbol.
摘要翻译：提供了一种具有包括伽罗瓦域元素的奇偶校验矩阵的线性码随机解码的解码方法和系统。一组编码样本的每个编码样本首先按照与编码样本集合的噪声电平成比例的缩放因子来缩放。然后将每个经缩放的编码样本转换成相应的概率。对于每个概率，相应的概率消息是通过将每个概率编码为符号或比特的序列而生成的。然后将每个概率消息提供给用于随机解码的逻辑电路的相应可变节点。逻辑电路表示线性码的奇偶校验矩阵的因子图。使用逻辑电路，通过对可变节点处的每个接收到的符号执行相等函数，在置换节点乘法和除法之一以及奇偶校验节点处执行奇偶校验功能，将每个概率消息传递通过因子图，其中每个可变节点根据每个接收的符号提供输出符号。

7. 发明授权

US11248938B2 Universal mounting system for insulated instruments 有权
公开(公告)号：US11248938B2
公开(公告)日：2022-02-15
申请号：US16457420
申请日：2019-06-28
申请人： Marcus C. McCarter , Warren J. Gross
发明人： Marcus C. McCarter , Warren J. Gross
IPC分类号： G01D11/30 , B63B35/44 , G01D11/24 , F16L3/22 , G01L19/04
摘要： A universal mounting system for insulated instruments includes a mounting plate which engages openings in mating parts of a self-supporting insulated enclosure. The plate supports the instrument and the enclosure independently and allows all connections to the interior of the enclosure to be made through the plate. The plate is bent to an L-shape, with one leg supported by a support structure and the other leg supporting the instrument and enclosure. A termination of a traced tubing system is housed in an enclosure mounted to an opposite side of the mounting plate. The mounting plate includes a collar, cutouts in mating sections of the enclosure fitting over the collar to mount the enclosure to the mounting plate. Illustratively, the mounting plate includes a mount plate portion connected to a supporting structure, and an instrument plate mounted to the instrument.

8. 发明申请

US20080294970A1 Method for implementing stochastic equality nodes 有权
标题翻译：实现随机均等节点的方法
公开(公告)号：US20080294970A1
公开(公告)日：2008-11-27
申请号：US12153749
申请日：2008-05-23
申请人： Warren J. Gross , Shie Mannor , Saeed Sharifi Tehrani
发明人： Warren J. Gross , Shie Mannor , Saeed Sharifi Tehrani
IPC分类号： G06F11/00
CPC分类号： H03M13/1102
摘要： The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.
摘要翻译：本发明涉及一种具有奇偶校验矩阵的线性块码随机解码的解码方法和系统。一组编码样本的每个编码样本被转换成相应的概率。对于每个概率，相应的概率消息是通过将每个概率编码为数字符号序列而生成的。然后将每个概率消息提供给用于随机解码的逻辑电路的相应节点。逻辑电路表示线性块码的奇偶校验矩阵的因子图。使用逻辑电路处理每个概率消息以确定信息符号的估计序列。如果等式节点处于保持状态，则从相应的存储器提供所选择的符号，相应的存储器当相同处于保持状态以外的状态时，通过存储来自等式节点的输出符号来更新。

9. 发明申请

US20200001951A1 UNIVERSAL MOUNTING SYSTEM FOR INSULATED INSTRUMENTS 审中-公开
公开(公告)号：US20200001951A1
公开(公告)日：2020-01-02
申请号：US16457420
申请日：2019-06-28
申请人： Marcus C. McCarter , Warren J. Gross
发明人： Marcus C. McCarter , Warren J. Gross
IPC分类号： B63B35/44 , G01D11/30 , G01D11/24
摘要： A universal mounting system for insulated instruments includes a mounting plate which engages openings in mating parts of a self-supporting insulated enclosure. The plate supports the instrument and the enclosure independently and allows all connections to the interior of the enclosure to be made through the plate. The plate is bent to an L-shape, with one leg supported by a support structure and the other leg supporting the instrument and enclosure. A termination of a traced tubing system is housed in an enclosure mounted to an opposite side of the mounting plate. The mounting plate includes a collar, cutouts in mating sections of the enclosure fitting over the collar to mount the enclosure to the mounting plate. Illustratively, the mounting plate includes a mount plate portion connected to a supporting structure, and an instrument plate mounted to the instrument.

10. 发明授权

US08108760B2 Decoding of linear codes with parity check matrix 有权
标题翻译：用奇偶校验矩阵解码线性码
公开(公告)号：US08108760B2
公开(公告)日：2012-01-31
申请号：US12503607
申请日：2009-07-15
申请人： Warren J. Gross , Shie Mannor , Gabi Sarkis
发明人： Warren J. Gross , Shie Mannor , Gabi Sarkis
IPC分类号： H03M13/00
CPC分类号： H03M13/1171 , H04L1/0057
摘要： A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code. Using the logic circuitry each probability message is passed through the factor graph by performing for each received symbol at the variable nodes the equality function, at the permutation nodes one of multiplication and division, and at the parity check nodes the parity check function, wherein each of the variable nodes provides an output symbol in dependence upon each received symbol.
摘要翻译：提供了一种具有包括伽罗瓦域元素的奇偶校验矩阵的线性码随机解码的解码方法和系统。一组编码样本的每个编码样本首先按照与编码样本集合的噪声电平成比例的缩放因子来缩放。然后将每个经缩放的编码样本转换成相应的概率。对于每个概率，相应的概率消息是通过将每个概率编码为符号或比特的序列而生成的。然后将每个概率消息提供给用于随机解码的逻辑电路的相应可变节点。逻辑电路表示线性码的奇偶校验矩阵的因子图。使用逻辑电路，通过对可变节点处的每个接收到的符号执行相等函数，在置换节点乘法和除法之一以及奇偶校验节点处执行奇偶校验功能，将每个概率消息传递通过因子图，其中每个可变节点根据每个接收的符号提供输出符号。

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