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1. 发明授权

US09997534B2 Vertical memory devices 有权
公开(公告)号：US09997534B2
公开(公告)日：2018-06-12
申请号：US15155732
申请日：2016-05-16
申请人： Yong-Hoon Son , Kyung-Hyun Kim , Byeong-Ju Kim , Phil-Ouk Nam , Kwang Chul Park , Yeon-Sil Sohn , Jin-I Lee , Jong-Heun Lim , Won-Bong Jung , Kohji Kanamori
发明人： Yong-Hoon Son , Kyung-Hyun Kim , Byeong-Ju Kim , Phil-Ouk Nam , Kwang Chul Park , Yeon-Sil Sohn , Jin-I Lee , Jong-Heun Lim , Won-Bong Jung , Kohji Kanamori
IPC分类号： H01L29/792 , H01L27/11582 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/528
摘要： A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

2. 发明授权

US10079203B2 Vertical memory devices and methods of manufacturing the same 有权
公开(公告)号：US10079203B2
公开(公告)日：2018-09-18
申请号：US15271605
申请日：2016-09-21
申请人： Yong-Hoon Son , Cha-Dong Yeo , Han-Mei Choi , Kyung-Hyun Kim , Phil-Ouk Nam , Kwang-Chul Park , Yeon-Sil Sohn , Jin-I Lee , Won-Bong Jung
发明人： Yong-Hoon Son , Cha-Dong Yeo , Han-Mei Choi , Kyung-Hyun Kim , Phil-Ouk Nam , Kwang-Chul Park , Yeon-Sil Sohn , Jin-I Lee , Won-Bong Jung
IPC分类号： H01L23/522 , H01L27/11582 , H01L21/768 , H01L27/11565 , H01L27/11575 , H01L27/1157
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76877 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.

3. 发明申请

US20170084532A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20170084532A1
公开(公告)日：2017-03-23
申请号：US15271605
申请日：2016-09-21
申请人： Yong-Hoon SON , Cha-Dong YEO , Han-Mei CHOI , Kyung-Hyun KIM , Phil-Ouk NAM , Kwang-Chui PARK , Yeon-Sil SOHN , Jin-I LEE , Won-Bong JUNG
发明人： Yong-Hoon SON , Cha-Dong YEO , Han-Mei CHOI , Kyung-Hyun KIM , Phil-Ouk NAM , Kwang-Chui PARK , Yeon-Sil SOHN , Jin-I LEE , Won-Bong JUNG
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532 , H01L27/115 , H01L23/528
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76877 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.

4. 发明申请

US20170033119A1 Vertical Non-Volatile Semiconductor Devices 审中-公开
标题翻译：垂直非易失性半导体器件
公开(公告)号：US20170033119A1
公开(公告)日：2017-02-02
申请号：US15165123
申请日：2016-05-26
申请人： Kwang Chul Park , Jang Gn YUN , Won Bong JUNG
发明人： Kwang Chul Park , Jang Gn YUN , Won Bong JUNG
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157
摘要： Semiconductor device are provided including a stacked structure having gate electrodes and interlayer insulating layers alternately stacked on a substrate; channel holes extending perpendicular to the substrate through the stacked structure and including channel regions therein; and horizontal parts at lower portions of the stacked structure and including areas in which the channel regions are horizontally elongated from the channel holes. The horizontal parts surround respective channel holes and are connected to each other between at a least portion of the channel holes.
摘要翻译：提供半导体器件，其包括层叠结构，其具有交替层叠在基板上的栅电极和层间绝缘层; 通孔穿过层叠结构垂直于衬底延伸并且在其中包括沟道区域; 以及层叠结构的下部的水平部分，并且包括沟道区域从通道孔水平伸长的区域。水平部分围绕相应的通道孔，并且在通道孔的至少部分之间彼此连接。

5. 发明授权

US08883588B2 Semiconductor devices and methods of manufacturing the semiconductor devices 有权
标题翻译：半导体器件和制造半导体器件的方法
公开(公告)号：US08883588B2
公开(公告)日：2014-11-11
申请号：US13599233
申请日：2012-08-30
申请人： Sung-Soo Ahn , O Ik Kwon , Bum-Soo Kim , Hyun-Sung Kim , Kyoung-Sub Shin , Min-Kyung Yun , Seung-Pil Chung , Won-Bong Jung
发明人： Sung-Soo Ahn , O Ik Kwon , Bum-Soo Kim , Hyun-Sung Kim , Kyoung-Sub Shin , Min-Kyung Yun , Seung-Pil Chung , Won-Bong Jung
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/7883 , H01L21/7682 , H01L27/11521 , H01L29/42324 , H01L29/42364 , H01L29/66825 , H01L29/7881
摘要： A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
摘要翻译：一种制造半导体器件的方法，所述方法包括在衬底的上表面上形成隧道绝缘层，在隧道绝缘层的上表面上形成栅极图案，在栅极图案的侧壁上形成覆盖层图案，并且在隧道绝缘层的上表面，蚀刻未被栅极图案或覆盖层图案覆盖的隧道绝缘层的一部分以形成隧道绝缘层图案，并且在衬底的上表面上形成第一绝缘层以覆盖栅极图案，覆盖层图案和隧道绝缘层图案，其中第一绝缘层在封盖层图案之间具有气隙。

6. 发明申请

US20170069637A1 NONVOLATILE MEMORY DEVICE AND A METHOD FOR FABRICATING THE SAME 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US20170069637A1
公开(公告)日：2017-03-09
申请号：US15251580
申请日：2016-08-30
申请人： YONG-HOON SON , JONG-WON KIM , CHANG-SEOK KANG , YOUNG-WOO PARK , JAE-DUK LEE , KYUNG-HYUN KIM , BYEONG-JU KIM , PHIL-OUK NAM , KWANG-CHUL PARK , YEON-SIL SOHN , JIN-I LEE , WON-BONG JUNG
发明人： YONG-HOON SON , JONG-WON KIM , CHANG-SEOK KANG , YOUNG-WOO PARK , JAE-DUK LEE , KYUNG-HYUN KIM , BYEONG-JU KIM , PHIL-OUK NAM , KWANG-CHUL PARK , YEON-SIL SOHN , JIN-I LEE , WON-BONG JUNG
IPC分类号： H01L27/115 , H01L29/66
CPC分类号： H01L27/1157 , H01L27/11565 , H01L27/11582 , H01L29/66833
摘要： A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.
摘要翻译：非易失性存储器件包括设置在衬底上并从衬底垂直延伸的导线，设置在衬底上并从衬底垂直延伸的第一沟道层，其中第一沟道层与导电线间隔开，第二沟道层，其中所述第二沟道层设置在所述第一沟道层和所述导电线之间;第一栅极，设置在所述导电线和所述第二沟道层之间，其中所述第一栅电极包括第一部分，所述第一部分具有第一厚度和具有不同于第一厚度的第二厚度的第二部分，以及设置在第一沟道层和第二沟道层之间的第二栅电极，其中第二栅电极具有第二厚度。

7. 发明申请

US20160343730A1 Vertical Memory Devices 有权
标题翻译：垂直存储器件
公开(公告)号：US20160343730A1
公开(公告)日：2016-11-24
申请号：US15155732
申请日：2016-05-16
申请人： Yong-Hoon Son , Kyung-Hyun KIM , Byeong-Ju KIM , Phil-Ouk NAM , Kwang Chul PARK , Yeon-Sil SOHN , Jin-I LEE , Jong-Heun LIM , Won-Bong JUNG , Kohji KANAMORI
发明人： Yong-Hoon Son , Kyung-Hyun KIM , Byeong-Ju KIM , Phil-Ouk NAM , Kwang Chul PARK , Yeon-Sil SOHN , Jin-I LEE , Jong-Heun LIM , Won-Bong JUNG , Kohji KANAMORI
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/528
摘要： A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.
摘要翻译：垂直存储器件包括衬底，衬底上的通道，相对于衬底的顶表面在垂直方向上延伸，并且在通道的下部包括突起，所述突起在平行方向上相对于到基板的顶面，连接突起和基板的半导体图案，以及在垂直方向上彼此堆叠和间隔开的栅极线，突起和半导体图案上的栅极线并围绕通道。

8. 发明申请

US20130134496A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20130134496A1
公开(公告)日：2013-05-30
申请号：US13599233
申请日：2012-08-30
申请人： Sung-Soo AHN , O IK KWON , Bum-Soo KIM , Hyun-Sung KIM , Kyoung-Sub SHIN , Min-Kyung YUN , Seung-Pil CHUNG , Won-Bong JUNG
发明人： Sung-Soo AHN , O IK KWON , Bum-Soo KIM , Hyun-Sung KIM , Kyoung-Sub SHIN , Min-Kyung YUN , Seung-Pil CHUNG , Won-Bong JUNG
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L29/7883 , H01L21/7682 , H01L27/11521 , H01L29/42324 , H01L29/42364 , H01L29/66825 , H01L29/7881
摘要： A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.
摘要翻译：一种制造半导体器件的方法，所述方法包括在衬底的上表面上形成隧道绝缘层，在隧道绝缘层的上表面上形成栅极图案，在栅极图案的侧壁上形成覆盖层图案，并且在隧道绝缘层的上表面，蚀刻未被栅极图案或覆盖层图案覆盖的隧道绝缘层的一部分以形成隧道绝缘层图案，并且在衬底的上表面上形成第一绝缘层以覆盖栅极图案，覆盖层图案和隧道绝缘层图案，其中第一绝缘层在封盖层图案之间具有气隙。

9. 发明申请

US20160358927A1 MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20160358927A1
公开(公告)日：2016-12-08
申请号：US15049160
申请日：2016-02-22
申请人： Phil Ouk NAM , Yong Hoon SON , Kyung Hyun KIM , Byeong Ju KIM , Kwang Chul PARK , Yeon Sil SOHN , Jin I LEE , Jong Heun LIM , Won Bong JUNG
发明人： Phil Ouk NAM , Yong Hoon SON , Kyung Hyun KIM , Byeong Ju KIM , Kwang Chul PARK , Yeon Sil SOHN , Jin I LEE , Jong Heun LIM , Won Bong JUNG
IPC分类号： H01L27/115 , H01L21/02
CPC分类号： H01L27/1157 , H01L21/02667 , H01L21/02675 , H01L27/11573 , H01L27/11582
摘要： A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.
摘要翻译：一种存储器件，包括第一存储区域，包括第一衬底，第一衬底上的多个第一半导体器件以及覆盖多个第一半导体器件的第一层间绝缘层; 以及第二存储区域，包括在所述第一层间绝缘层上的第二衬底和所述第二衬底上的多个第二半导体器件，所述第二衬底包括在所述第一层间绝缘层中的多个沟槽中的第一区域和包括晶粒从第一区域延伸，第二区域位于第一层间绝缘层的上表面上。

10. 发明授权

US07088047B2 Inductively coupled plasma generator having low aspect ratio 失效
标题翻译：具有低纵横比的电感耦合等离子体发生器
公开(公告)号：US07088047B2
公开(公告)日：2006-08-08
申请号：US11043207
申请日：2005-01-26
申请人： Yong-Kwan Lee , Won-Bong Jung , Sang-Won Lee , Sae-Hoon Uhm , Dong-Seok Lee
发明人： Yong-Kwan Lee , Won-Bong Jung , Sang-Won Lee , Sae-Hoon Uhm , Dong-Seok Lee
IPC分类号： H01J7/24 , B44C1/22 , C23C16/00
CPC分类号： H01J37/321 , H05H1/46
摘要： An inductively coupled plasma generator having a lower aspect ratio reaction gas, comprising a chamber having a gas inlet through which a reaction gas is supplied, a vacuum pump for maintaining the inside of the chamber vacuum and a gas outlet for exhausting the reaction gas after completion of the reaction, a chuck for mounting a target material to be processed inside the chamber, and an antenna to which high-frequency power is applied, the antenna provided at the upper and lateral portions of the chamber, wherein the antenna has parallel antenna elements in which a discharge of a high frequency can be allowed and impedance is low to ensure a low electron temperature, the antenna is disposed such that a powered end of each of the antenna elements and a ground end of each of the antenna elements opposite to the powered end are symmetrical in view of the center of an imaginary circle formed by the antenna to establish rotation symmetry of plasma density profiles, the antenna elements are twisted in a helical manner, and the powered end of each of the antenna elements is positioned to be far from the chamber and the ground end of each of the antenna elements is positioned to be close to the chamber, thereby compensating for a drop in the plasma density due to ion loss occurring at the powered end.
摘要翻译：一种具有较低纵横比的反应气体的电感耦合等离子体发生器，包括具有供应反应气体的气体入口的室，用于维持室内真空的真空泵和用于在完成后排出反应气体的气体出口的反应，用于在室内安装待处理的目标材料的卡盘以及设置在室的上部和外侧部分处的高频电力的天线，其中天线具有平行的天线元件其中可以允许高频放电并且阻抗低以确保低电子温度，天线被布置成使得每个天线元件的动力端和每个天线元件的接地端与鉴于由天线形成的假想圆的中心，以建立等离子体密度分布的旋转对称性，动力端对称，天线元件ar e以螺旋方式扭绞，并且每个天线元件的动力端定位成远离腔室，并且每个天线元件的接地端被定位成靠近腔室，从而补偿了下降由于在动力端发生离子损失引起的等离子体密度。

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