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1. 发明申请

WO2019204525A1 A MEMORY DEVICE COMPRISING AN ELECTRICALLY FLOATING BODY TRANSISTOR 审中-公开
公开(公告)号：WO2019204525A1
公开(公告)日：2019-10-24
申请号：PCT/US2019/027994
申请日：2019-04-17
申请人： ZENO SEMICONDUCTOR, INC. , WIDJAJA, Yuniarto , HAN, Jin-Woo
发明人： WIDJAJA, Yuniarto , HAN, Jin-Woo
IPC分类号： H01L27/11524 , H01L27/11529 , H01L27/11551 , H01L27/11548
摘要： A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

2. 发明申请

WO2008136813A2 SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING 审中-公开
标题翻译：具有两种挥发性和非挥发性功能的半导体存储器和操作方法
公开(公告)号：WO2008136813A2
公开(公告)日：2008-11-13
申请号：PCT/US2007024544
申请日：2007-11-29
申请人： WIDJAJA YUNIARTO
发明人： WIDJAJA YUNIARTO
IPC分类号： H01L29/788 , G11C16/04
CPC分类号： H01L29/7841 , G11C14/00 , H01L27/115 , H01L29/66825 , H01L29/7881
摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.
摘要翻译：具有易失性和非易失性模式和操作方法的半导体存储器。半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在基板的第二位置处嵌入基板并具有第二导电类型，使得具有第一导电类型的基板的至少一部分位于第一和第二位置之间，并且用作浮体以存储易失性存储器中的数据; 位于所述第一和第二位置之间并位于所述基板的表面之上并且通过绝缘层与所述表面绝缘的浮栅或捕获层; 浮动栅极或俘获层被配置为在中断对存储器单元的电力时，接收由易失性存储器存储的数据的传输并将数据作为非易失性存储器存储在浮动栅极或俘获层中; 以及位于浮置栅极或俘获层上方的控制栅极和位于浮置栅极或捕获层与控制栅极之间的第二绝缘层。

3. 发明申请

WO2013123415A1 MEMORY CELL COMPRISING FIRST AND SECOND TRANSISTORS AND METHODS OF OPERATING 审中-公开
标题翻译：包含第一和第二晶体管的存储单元和操作方法
公开(公告)号：WO2013123415A1
公开(公告)日：2013-08-22
申请号：PCT/US2013/026466
申请日：2013-02-15
申请人： ZENO SEMICONDUCTOR, INC. , WIDJAJA, Yuniarto , OR-BACH, Zvi
发明人： WIDJAJA, Yuniarto , OR-BACH, Zvi
IPC分类号： G11C11/40 , H01L21/8239 , H01L27/10
CPC分类号： G11C7/02 , G11C11/403 , G11C2211/4016 , H01L27/10802 , H01L29/7841
摘要： Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.
摘要翻译：公开了半导体存储器单元，阵列和操作方法。在一种情况下，存储单元包括双稳态浮体晶体管和存取器件; 其中所述双稳态浮体晶体管和所述存取装置串联电连接。

4. 发明申请

WO2011097592A1 SEMICONDUCTOR MEMORY DEVICE HAVING ELECTRICALLY FLOATING BODY TRANSISTOR, AND HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD 审中-公开
标题翻译：具有电浮标体晶体管的半导体存储器件，并具有两个挥发性和非挥发性功能和方法
公开(公告)号：WO2011097592A1
公开(公告)日：2011-08-11
申请号：PCT/US2011/023947
申请日：2011-02-07
申请人： ZENO SEMICONDUCTOR , INC. , WIDJAJA, Yuniarto , OR-BACH, Zvi
发明人： WIDJAJA, Yuniarto , OR-BACH, Zvi
IPC分类号： G11C11/34
CPC分类号： G11C14/0018 , G11C11/404 , G11C11/565 , G11C16/0416 , G11C16/0433 , G11C16/06 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/42328 , H01L29/4916 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/788 , H01L29/7881
摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
摘要翻译：半导体存储单元包括被配置为被充电到指示存储单元的状态的电平的浮动体区域; 与所述浮体区域电接触的第一区域; 与所述浮体区域电接触并与所述第一区域间隔开的第二区域; 以及位于所述第一和第二区域之间的门。单元可以是多级单元。公开了用于制造存储器件的存储器单元阵列。还提供了操作存储单元的方法。

5. 发明申请

WO2008136813A3 SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING 审中-公开
公开(公告)号：WO2008136813A3
公开(公告)日：2008-11-13
申请号：PCT/US2007/024544
申请日：2007-11-29
申请人： WIDJAJA, Yuniarto
发明人： WIDJAJA, Yuniarto
IPC分类号： G11C11/34
摘要： Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a floating gate or trapping layer positioned in between first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell.

6. 发明申请

WO2016176248A1 A MOSFET AND MEMORY CELL HAVING IMPROVED DRAIN CURRENT THROUGH BACK BIAS APPLICATION 审中-公开
标题翻译：具有通过反向偏置应用改进漏电流的MOSFET和存储器单元
公开(公告)号：WO2016176248A1
公开(公告)日：2016-11-03
申请号：PCT/US2016/029436
申请日：2016-04-27
申请人： ZENO SEMICONDUCTOR, INC. , HAN, Jin-woo , WIDJAJA, Yuniarto , OR-BACH, Zvi , MAHESHWARI, Dinesh
发明人： HAN, Jin-woo , WIDJAJA, Yuniarto , OR-BACH, Zvi , MAHESHWARI, Dinesh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/28273 , H01L21/28282 , H01L21/761 , H01L21/76224 , H01L21/823821 , H01L21/823892 , H01L27/092 , H01L27/0924 , H01L29/1083 , H01L29/1087 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.
摘要翻译：已经描述了通过MOSFET的本征双极结型晶体管（BJT）获得的具有增加的通态电流的半导体金属氧化物半导体场效应晶体管（MOSFET）晶体管。提供了操作MOS晶体管的方法。

7. 发明专利

TWI694525B 通過施加回饋偏壓提高漏極電流的金屬氧化物半導體場效應電晶體（ＭＯＳＦＥＴ）和存儲單元有权
简体标题：通过施加回馈偏压提高漏极电流的金属氧化物半导体场效应晶体管（ＭＯＳＦＥＴ）和存储单元
公开(公告)号：TWI694525B
公开(公告)日：2020-05-21
申请号：TW105113137
申请日：2016-04-27
申请人：美商季諾半導體股份有限公司 , ZENO SEMICONDUCTOR, INC. , 韓珍優 , HAN, JIN-WOO , 魏迪傑尤諾歐德 , WIDJAJA, YUNIARTO , 歐貝克凡 , OR-BACH, ZVI , 梅許瓦迪內希 , MAHESHWARI, DINESH
发明人：韓珍優 , HAN, JIN-WOO , 魏迪傑尤諾歐德 , WIDJAJA, YUNIARTO , 歐貝克凡 , OR-BACH, ZVI , 梅許瓦迪內希 , MAHESHWARI, DINESH
IPC分类号： H01L21/336 , H01L21/8238

8. 发明专利

TW201703157A 通過施加回饋偏壓提高漏極電流的金屬氧化物半導體場效應電晶體(MOSFET)和存儲單元审中-公开
简体标题：通过施加回馈偏压提高漏极电流的金属氧化物半导体场效应晶体管(MOSFET)和存储单元
公开(公告)号：TW201703157A
公开(公告)日：2017-01-16
申请号：TW105113137
申请日：2016-04-27
申请人：季諾半導體股份有限公司 , ZENO SEMICONDUCTOR, INC. , 韓珍優 , HAN, JIN-WOO , 魏迪傑尤諾歐德 , WIDJAJA, YUNIARTO , 歐貝克凡 , OR-BACH, ZVI , 梅許瓦迪內希 , MAHESHWARI, DINESH
发明人：韓珍優 , HAN, JIN-WOO , 魏迪傑尤諾歐德 , WIDJAJA, YUNIARTO , 歐貝克凡 , OR-BACH, ZVI , 梅許瓦迪內希 , MAHESHWARI, DINESH
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/78 , H01L21/28273 , H01L21/28282 , H01L21/761 , H01L21/76224 , H01L21/823821 , H01L21/823892 , H01L27/092 , H01L27/0924 , H01L29/1083 , H01L29/1087 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/785 , H01L29/7881 , H01L29/792
摘要：本文介紹了一個金屬氧化物半導體場效應電晶體(MOSFET)，通過MOSFET固有的雙極面結型電晶體(BJT)提高導通電流。本文還提供了MOS電晶體的工作方法。
简体摘要：本文介绍了一个金属氧化物半导体场效应晶体管(MOSFET)，通过MOSFET固有的双极面结型晶体管(BJT)提高导通电流。本文还提供了MOS晶体管的工作方法。

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