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1. 发明申请

WO2011119941A1 LOW-POWER 5T SRAM WITH IMPROVED STABILITY AND REDUCED BITCELL SIZE 审中-公开
标题翻译：低功耗5T SRAM，具有改进的稳定性和降低的BITCELL SIZE
公开(公告)号：WO2011119941A1
公开(公告)日：2011-09-29
申请号：PCT/US2011/029970
申请日：2011-03-25
申请人： QUALCOMM Incorporated , JUNG, Seong-Ook , PARK, Hyunkook , SONG, Seung-Chul , ABU-RAHMA, Mohamed Hassan , GE, Lixin , WANG, Zhongze , HAN, Beom-Mo
发明人： JUNG, Seong-Ook , PARK, Hyunkook , SONG, Seung-Chul , ABU-RAHMA, Mohamed Hassan , GE, Lixin , WANG, Zhongze , HAN, Beom-Mo
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM (400) includes a storage element (402) for storing data, wherein the storage element is coupled a first voltage and a ground voltage. The storage element can include symmetrically sized cross - coupled inverters. A single access transistor (M5 ) controls read and write operations on the storage element (402). Control logic (M6,M6') is configured to generate a value of the first voltage for a write operation that is different from the value of the first voltage for a read operation.
摘要翻译： 5晶体管静态随机存取存储器（5T SRAM）设计用于减小电池尺寸和对工艺变化的抗扰性。 5T SRAM（400）包括用于存储数据的存储元件（402），其中存储元件耦合第一电压和接地电压。存储元件可以包括对称尺寸的交叉耦合的反相器。单个存取晶体管（M5）控制对存储元件（402）的读取和写入操作。控制逻辑（M6，M6'）被配置为为读操作产生不同于第一电压值的写操作的第一电压值。

2. 发明申请

WO2011066322A3 IMPROVED EDRAM ARCHITECTURE 审中-公开
标题翻译：改进的EDRAM架构
公开(公告)号：WO2011066322A3
公开(公告)日：2011-09-15
申请号：PCT/US2010057888
申请日：2010-11-23
申请人： QUALCOMM INC , KANG WOOTAG , WANG ZHONGZE
发明人： KANG WOOTAG , WANG ZHONGZE
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10894 , H01L27/10811 , H01L27/10897
摘要： A process for manufacturing an eDRAM device (300) comprises fabricating semiconductor features (304 a-e) on a semiconductor substrate, the semiconductor substrate including a DRAM area (301) and logic area (302). The process also includes fabricating a first conductive layer (Ml) in the DRAM area and in the logic area, the first conductive layer in communication with a first group of the semiconductor features. After fabricating the first conductive layer, a storage component (312,313) is fabricated in communication with a second group of the semiconductor features within the DRAM area.
摘要翻译：一种制造eDRAM器件（300）的方法包括在半导体衬底上制造半导体特征（304a-e），所述半导体衬底包括DRAM区域（301）和逻辑区域（302）。该工艺还包括在DRAM区域和逻辑区域中制造第一导电层（M1），第一导电层与第一组半导体特征通信。在制造第一导电层之后，制造与DRAM区域内的第二组半导体特征通信的存储部件（312,313）。

3. 发明申请

WO2011066322A2 IMPROVED EDRAM ARCHITECTURE 审中-公开
标题翻译：改进的EDRAM架构
公开(公告)号：WO2011066322A2
公开(公告)日：2011-06-03
申请号：PCT/US2010/057888
申请日：2010-11-23
申请人： QUALCOMM Incorporated , KANG, Wootag , WANG, Zhongze
发明人： KANG, Wootag , WANG, Zhongze
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L27/10811 , H01L27/10897
摘要： A process for manufacturing an eDRAM device comprises fabricating semiconductor features on a semiconductor substrate, the semiconductor substrate including a DRAM area and logic area. The process also includes fabricating a first conductive layer in the DRAM area and in the logic area, the first conductive layer in communication with a first group of the semiconductor features. After fabricating the first conductive layer, a storage component is fabricated in communication with a second group of the semiconductor features within the DRAM area.
摘要翻译：一种制造eDRAM器件的方法包括在半导体衬底上制造半导体器件，该半导体衬底包括一个DRAM区域和逻辑区域。该工艺还包括在DRAM区域和逻辑区域中制造第一导电层，第一导电层与第一组半导体特征通信。在制造第一导电层之后，制造与DRAM区域内的第二组半导体特征通信的存储部件。

4. 发明申请

WO2012061666A1 STABLE SRAM BITCELL DESIGN UTILIZING INDEPENDENT GATE FINFET 审中-公开
标题翻译： STABLE SRAM BITCELL设计利用独立的栅极FINFET
公开(公告)号：WO2012061666A1
公开(公告)日：2012-05-10
申请号：PCT/US2011/059247
申请日：2011-11-04
申请人： QUALCOMM INCORPORATED , JUNG, Seong-Ook , KANG, Mingu , PARK, Hyunkook , SONG, Seung-Chul , ABU-RAHAMA, Mohamed , HAN, Beom-Mo , GE, Lixin , WANG, Zhongze
发明人： JUNG, Seong-Ook , KANG, Mingu , PARK, Hyunkook , SONG, Seung-Chul , ABU-RAHAMA, Mohamed , HAN, Beom-Mo , GE, Lixin , WANG, Zhongze
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/4125 , H01L27/1104 , Y10T29/49117
摘要： Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.
摘要翻译：利用独立栅极FinFET架构的稳定SRAM单元提供了诸如读静态噪声余量（RSNM）和写噪声余量（WNM）的器件参数中的常规SRAM单元的改进。示例性SRAM单元包括一对存储节点，一对位线，一对上拉器件，一对下拉器件和一对通栅器件。第一控制信号和第二控制信号被配置为调整传递门装置的驱动强度，并且第三控制信号被配置为调节上拉装置的驱动强度，其中第一控制信号被正交地传送到位线方向，并且第二和第三控制信号沿与位线方向相同的方向路由。通过在读写操作期间调整上拉和通过栅极器件的驱动强度，RSNM和WNM得到了改进。

5. 发明申请

WO2009140612A1 TESTING A MEMORY DEVICE HAVING FIELD EFFECT TRANSISTORS SUBJECT TO THRESHOLD VOLTAGE SHIFTS CAUSED BY BIAS TEMPERATURE INSTABILITY 审中-公开
标题翻译：测试具有由偏置温度不稳定性引起的阈值电压变化的场效应晶体管的存储器件
公开(公告)号：WO2009140612A1
公开(公告)日：2009-11-19
申请号：PCT/US2009/044171
申请日：2009-05-15
申请人： QUALCOMM INCORPORATED , CHEN, Nan , LEE, Sian-Yee, Sean , JUNG, Seong-Ook , WANG, Zhongze
发明人： CHEN, Nan , LEE, Sian-Yee, Sean , JUNG, Seong-Ook , WANG, Zhongze
IPC分类号： G11C29/10 , G11C29/50
CPC分类号： G11C29/50 , G11C11/41 , G11C29/10 , G11C29/12005
摘要： A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.
摘要翻译：在第一电源电压电平下为存储器件设置电源电压。响应于设置电源电压，以第一电源电压电平将测试数据写入存储器件。响应于写入测试数据，存储器件的电源电压降低到低于第一电源电压电平的第二电源电压电平。响应于降低电源电压，在第二电源电压电平下从存储器件读取测试数据。响应于读取测试数据，存储器件的电源电压增加到高于第二电源电压电平的第三电源电压电平。响应于增加电源电压，在第三电源电压电平下从存储器件读取测试数据。响应于以第三电源电压从存储器件读取测试数据，将以第一电源电压电平写入存储器件的测试数据与从第三电源电压电平读出的测试数据进行比较。

6. 发明申请

WO2011127054A1 PROGRAMMABLE TRACKING CIRCUIT FOR TRACKING SEMICONDUCTOR MEMORY READ CURRENT 审中-公开
标题翻译：用于跟踪半导体存储器的可编程跟踪电路读取电流
公开(公告)号：WO2011127054A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/031251
申请日：2011-04-05
申请人： QUALCOMM Incorporated , WANG, Zhongze
发明人： WANG, Zhongze
IPC分类号： G11C7/08 , G11C7/22 , G11C11/419
CPC分类号： G11C7/08 , G11C7/22 , G11C7/227 , G11C11/419
摘要： One example memory device includes a memory array, a sense amplifier, and a tracking circuit. The memory array is formed of a plurality of memory cells. The sense amplifier is for accessing the memory array. The tracking circuit is for tracking memory read current of the memory array. The tracking circuit comprises one or more columns of tracking cells. Each column is coupled to a corresponding bit line to provide a drive current on the bit line for triggering a memory read operation by the sense amplifier. At least one of the columns comprises two tracking cells connected in series to each other.
摘要翻译：一个示例性存储器件包括存储器阵列，读出放大器和跟踪电路。存储器阵列由多个存储单元形成。读出放大器用于访问存储器阵列。跟踪电路用于跟踪存储器阵列的存储器读取电流。跟踪电路包括一列或多列跟踪单元。每列耦合到对应的位线，以在位线上提供驱动电流，以触发读出放大器的存储器读取操作。至少一列包括彼此串联连接的两个跟踪单元。

7. 发明申请

WO2011097457A1 SYSTEMS AND METHODS FOR WRITING TO MULTIPLE PORT MEMORY CIRCUITS 审中-公开
标题翻译：用于写入多个端口存储器电路的系统和方法
公开(公告)号：WO2011097457A1
公开(公告)日：2011-08-11
申请号：PCT/US2011/023716
申请日：2011-02-04
申请人： QUALCOMM INCORPORATED , YANG, Haining , WANG, Zhongze , JUNG, ChangHo
发明人： YANG, Haining , WANG, Zhongze , JUNG, ChangHo
IPC分类号： G11C8/16 , G11C11/412
CPC分类号： G11C8/16 , G11C11/412
摘要： A multiple-port RAM circuit has a data-in line (DIN) coupled to multiple bit lines (a-bit, b-bit) and multiple bit line bars (a-bitb, b-bitb). The circuit also has multiple word lines (a-wl, b-wl). A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller (201) that enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell.
摘要翻译：多端口RAM电路具有耦合到多个位线（a位，b位）和多位线条（a-bitb，b-bitb）的数据输入线（DIN）。该电路还具有多个字线（a-wl，b-wl）。存储器单元耦合到位线，位线条和字线。该电路还包括控制器（201），其使得字线能够基本上同时将来自位线的值写入存储器单元。

8. 发明申请

WO2011084501A1 SYSTEMS AND METHODS EMPLOYING A PHYSICALLY ASYMMETRIC SEMICONDUCTOR DEVICE HAVING SYMMETRICAL ELECTRICAL BEHAVIOR 审中-公开
标题翻译：使用具有对称电气行为的物理非对称半导体器件的系统和方法
公开(公告)号：WO2011084501A1
公开(公告)日：2011-07-14
申请号：PCT/US2010/060546
申请日：2010-12-15
申请人： QUALCOMM INCORPORATED , YANG, Haining , GAN, Chock H. , WANG, Zhongze , HAN, Beom-Mo
发明人： YANG, Haining , GAN, Chock H. , WANG, Zhongze , HAN, Beom-Mo
IPC分类号： H01L21/8234 , H01L27/02 , H01L27/088
CPC分类号： H01L27/0207 , H01L21/823425 , H01L21/823475 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.
摘要翻译：一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

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