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1. 发明申请

US20090313457A1 System and Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register 有权
标题翻译：从多于一个寄存器扩展字段的数据包中提取字段的系统和方法
公开(公告)号：US20090313457A1
公开(公告)日：2009-12-17
申请号：US12544167
申请日：2009-08-19
申请人： Sol KATZMAN , Robert Gelinas , W. Patrick Hays
发明人： Sol KATZMAN , Robert Gelinas , W. Patrick Hays
IPC分类号： G06F9/30
CPC分类号： H04L29/06 , H04L69/22
摘要： Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field from a second general register designated as a second source register. The second instruction inserts any extracted field parts in a result register.
摘要翻译：允许使用两个指令从存储在一对寄存器中的数据中提取字段的系统和方法。第一指令从指定为第一源寄存器的第一寄存器中提取字段的任何部分，并执行从指定为第二源寄存器的第二通用寄存器中提取字段的任何部分的第二指令。第二条指令将任何提取的字段部分插入结果寄存器。

2. 发明申请

US20090210682A1 DATA TRANSFER BUS COMMUNICATION USING SINGLE REQUEST TO PERFORM COMMAND AND RETURN DATA TO DESTINATION INDICATED IN CONTEXT TO ALLOW THREAD CONTEXT SWITCH 有权
标题翻译：数据传输总线通信使用单次请求执行命令并将数据返回到目的地，显示为允许上下文切换
公开(公告)号：US20090210682A1
公开(公告)日：2009-08-20
申请号：US12429655
申请日：2009-04-24
申请人： Robert GELINAS , W. Patrick Hays , Sol Katzman , William J. Dally
发明人： Robert GELINAS , W. Patrick Hays , Sol Katzman , William J. Dally
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/461 , G06F9/48 , G06F9/4881
摘要： Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.
摘要翻译：用于在处理系统中的线程之间管理上下文切换的系统和方法。处理器可以使用单独的上下文寄存器在线程之间执行上下文切换。上下文切换允许处理器从处理等待数据的线程切换到准备进行额外处理的线程。该处理器包括具有条目的控制寄存器，其可以指示相关联的上下文正在等待来自外部源的数据。

3. 发明授权

US07529915B2 Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source 有权
标题翻译：具有多个上下文控制寄存器集的上下文切换处理器，包括写入地址寄存器，用于识别用于等待上下文存储来自外部源的返回数据的目的地寄存器
公开(公告)号：US07529915B2
公开(公告)日：2009-05-05
申请号：US11552640
申请日：2006-10-25
申请人： Robert Gelinas , W. Patrick Hays , Sol Katzman , William J. Dally
发明人： Robert Gelinas , W. Patrick Hays , Sol Katzman , William J. Dally
IPC分类号： G06F9/46
CPC分类号： G06F9/3004 , G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/461 , G06F9/48 , G06F9/4881
摘要： Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.
摘要翻译：用于在处理系统中的线程之间管理上下文切换的系统和方法。处理器可以使用单独的上下文寄存器在线程之间执行上下文切换上下文切换允许处理器从处理等待数据的线程切换到准备进行额外处理的线程。该处理器包括具有条目的控制寄存器，其可以指示相关联的上下文正在等待来自外部源的数据。

4. 发明授权

US07039060B2 System and method for extracting fields from packets having fields spread over more than one register 有权
公开(公告)号：US07039060B2
公开(公告)日：2006-05-02
申请号：US09799610
申请日：2001-03-07
申请人： Sol Katzman , Robert Gelinas , W. Patrick Hays
发明人： Sol Katzman , Robert Gelinas , W. Patrick Hays
IPC分类号： H04L12/28
CPC分类号： H04L29/06 , H04L69/22
摘要： Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field from a second general register designated as a second source register. The second instruction inserts any extracted field parts in a result register.

5. 发明授权

US07895423B2 Method for extracting fields from packets having fields spread over more than one register 有权
标题翻译：从多于一个寄存器分布的字段的数据包中提取字段的方法
公开(公告)号：US07895423B2
公开(公告)日：2011-02-22
申请号：US12544167
申请日：2009-08-19
申请人： Sol Katzman , Robert Gelinas , W. Patrick Hays
发明人： Sol Katzman , Robert Gelinas , W. Patrick Hays
IPC分类号： G06F7/00
CPC分类号： H04L29/06 , H04L69/22
摘要： Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field from a second general register designated as a second source register. The second instruction inserts any extracted field parts in a result register.
摘要翻译：允许使用两个指令从存储在一对寄存器中的数据中提取字段的系统和方法。第一指令从指定为第一源寄存器的第一寄存器中提取字段的任何部分，并执行从指定为第二源寄存器的第二通用寄存器中提取字段的任何部分的第二指令。第二条指令将任何提取的字段部分插入结果寄存器。

6. 发明授权

US07401205B1 High performance RISC instruction set digital signal processor having circular buffer and looping controls 有权
标题翻译：高性能RISC指令集数字信号处理器具有循环缓冲和循环控制
公开(公告)号：US07401205B1
公开(公告)日：2008-07-15
申请号：US09637500
申请日：2000-08-11
申请人： William J. Dally , W. Patrick Hays , Robert Gelinas , Sol Katzman , Sam Rosen , Staffan Ericsson
发明人： William J. Dally , W. Patrick Hays , Robert Gelinas , Sol Katzman , Sam Rosen , Staffan Ericsson
IPC分类号： G06F15/80 , G06F15/00
CPC分类号： G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F9/3017 , G06F9/30174 , G06F9/3836 , G06F9/3857 , G06F9/3885 , G06F9/3893 , G06F2207/3884
摘要： A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low-overhead interrupts.
摘要翻译：采用双乘积累管道的DSP超标量架构。双MAC管道允许在已建立的RISC指令集和扩展DSP指令集之间看起来较少的转换。提供可重定位的操作码，以便进一步扩展RISC指令集。 DSP超标量架构还提供具有硬件循环缓冲区支持的内存指针，可中断和嵌套的零开销循环计数器以及优先级低的开销中断。

7. 发明授权

US06651160B1 Register set extension for compressed instruction set 有权
标题翻译：用于压缩指令集的寄存器设置扩展
公开(公告)号：US06651160B1
公开(公告)日：2003-11-18
申请号：US09654064
申请日：2000-09-01
申请人： W. Patrick Hays
发明人： W. Patrick Hays
IPC分类号： G06F932
CPC分类号： G06F9/30138 , G06F9/30134 , G06F9/30156 , G06F9/30167 , G06F9/30178
摘要： Systems and methods for extending register addresses in compressed instruction sets are capable of executing extended register instructions that supplement the bits needed to address registers. The extended register instruction precedes corresponding standard instruction, and register the bits from the extend instruction are combined with register bits from the standard instruction to obtain a longer register address.
摘要翻译：用于在压缩指令集中扩展寄存器地址的系统和方法能够执行补充地址寄存器所需的位的扩展寄存器指令。扩展寄存器指令在相应的标准指令之前，寄存器的扩展指令中的位与标准指令的寄存器位组合，以获得更长的寄存器地址。

8. 发明授权

US09047093B2 Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities 有权
标题翻译：数据传输总线通信，通过发送附加标识符的请求指令来接收数据，表示处理器和线程上下文标识
公开(公告)号：US09047093B2
公开(公告)日：2015-06-02
申请号：US12429655
申请日：2009-04-24
申请人： Robert Gelinas , W. Patrick Hays , Sol Katzman , William J. Dally
发明人： Robert Gelinas , W. Patrick Hays , Sol Katzman , William J. Dally
IPC分类号： G06F9/46 , G06F9/312 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3004 , G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/461 , G06F9/48 , G06F9/4881
摘要： Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.
摘要翻译：用于在处理系统中的线程之间管理上下文切换的系统和方法。处理器可以使用单独的上下文寄存器在线程之间执行上下文切换。上下文切换允许处理器从处理等待数据的线程切换到准备进行额外处理的线程。该处理器包括具有条目的控制寄存器，其可以指示相关联的上下文正在等待来自外部源的数据。

9. 发明授权

US07162615B1 Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch 有权
标题翻译：数据传输总线通信使用单个请求执行命令并将数据返回到上下文中指示的目的地，以允许线程上下文切换
公开(公告)号：US07162615B1
公开(公告)日：2007-01-09
申请号：US09591510
申请日：2000-06-12
申请人： Robert Gelinas , W. Patrick Hays , Sol Katzman , William J. Dally
发明人： Robert Gelinas , W. Patrick Hays , Sol Katzman , William J. Dally
IPC分类号： G06F13/14
CPC分类号： G06F9/3004 , G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/461 , G06F9/48 , G06F9/4881
摘要： Systems and methods that allow for performing a single transaction that both instructs a device to perform an operation and return the resulting data to a processor without the processor having to send a separate request for the result. In accordance with the systems and methods, a bus controller generates a system bus operation that sends (to the device) a thread identifier and a data request formulated in one thread by a processor that context switches to a second thread.
摘要翻译：允许执行单个事务的系统和方法，其指示设备执行操作并将所得到的数据返回到处理器，而处理器不必发送针对结果的单独请求。根据系统和方法，总线控制器产生系统总线操作，该系统总线操作向上下文切换到第二线程的处理器发送（到设备）线程标识符和在一个线程中制定的数据请求。

10. 发明授权

US5926644A Instruction formats/instruction encoding 失效
标题翻译：指令格式/指令编码
公开(公告)号：US5926644A
公开(公告)日：1999-07-20
申请号：US427976
申请日：1995-04-21
申请人： W. Patrick Hays
发明人： W. Patrick Hays
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/30149 , G06F9/3802 , G06F9/3863
摘要： Single-instruction multiple-data is a new class of integrated video signal processors especially suited for real-time processing of two-dimensional images. The single-instruction, multiple-data architecture is adopted to exploit the high degree of parallelism inherent in many video signal processing algorithms. Features have been added to the architecture which support conditional execution and sequencing--an inherent limitation of traditional single-instruction multiple-data machines. A separate transfer engine offloads transaction processing from the execution core, allowing balancing of input/output and compute resources--a critical factor in optimizing performance for video processing. These features, coupled with a scalable architecture allow a united programming model and application driven performance.
摘要翻译：单指令多数据是一类新的集成视频信号处理器，特别适用于二维图像的实时处理。采用单指令多数据架构来开发许多视频信号处理算法中固有的高度并行度。功能已被添加到支持条件执行和排序的架构中，这是传统单指令多数据机器的固有局限性。单独的传输引擎从执行核心中卸载事务处理，允许平衡输入/输出和计算资源，这是优化视频处理性能的关键因素。这些功能与可扩展架构相结合，可以实现统一的编程模型和应用驱动的性能。

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