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1. 发明申请

US20090274017A1 MIXED-SIGNAL SINGLE-CHIP INTEGRATED SYSTEM ELECTRONICS FOR DATA STORAGE DEVICES 有权
标题翻译：混合信号单芯片集成系统电子数据存储设备
公开(公告)号：US20090274017A1
公开(公告)日：2009-11-05
申请号：US12435945
申请日：2009-05-05
申请人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, JR. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
发明人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, JR. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
IPC分类号： G11B21/10 , G06F13/38
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0673 , G06F3/0676 , G11B19/00 , G11B20/10009 , G11B25/043
摘要： An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.
摘要翻译：集成数据存储控制系统在单一集成电路中提供RDC，伺服逻辑，ATA接口，微处理器以及其它以前分立的组件，在一个高度集成的系统设计中。使用针对所有组件的单个集成电路技术类型（例如，数字CMOS）来呈现集成电路。模拟和数字电路的组合方式是消除或减少模拟电路组件在数字电路中的噪声或干扰。单个元件可以将它们的输出和输入多路复用在一起，使得各个元件可以选择性地切换（在测试模式期间），使得集成电路以与现有技术组件中的一个相同或相似的方式进行仿真或表现。本发明可以应用于磁性硬盘驱动器（HDD）或诸如软盘控制器，光盘驱动器（例如CD-ROM等），磁带驱动器和其他数据存储设备的其它类型的存储设备。

2. 发明授权

US4984151A Flexible, next-address generation microprogram sequencer 失效
标题翻译：灵活的下一个地址生成微程序排序器
公开(公告)号：US4984151A
公开(公告)日：1991-01-08
申请号：US227452
申请日：1988-08-02
申请人： Vineet Dujari
发明人： Vineet Dujari
IPC分类号： G06F9/26 , G06F9/32
CPC分类号： G06F9/324 , G06F9/265 , G06F9/321
摘要： A flexible, sequencer for providing next-address generation in the execution of a microprogram is described. The sequencer includes means for receiving an externally provided base address and an externally provided address offset value, a stack for storing return base address pointers, and means for storing a current program pointer counter address. The sequencer comprises means for selecting an address from one of a plurality of generated addresses and for providing the selected address as the next address in the execution of the microprogram, and means for generating the plurality of addresses including an address generation means selected from the group consisting of means for adding the address offset value with a stack stored return base address, means for adding the address offset value with the current program pointer counter address, means for selectively incrementing the selected address by one of a plurality of predetermined integral values, and means for selectively shifting the address offset value and for overlaying the external base address with the shifted address offset value, each means respectively generating one of the plurality of the generated addresses.
摘要翻译：描述了在执行微程序中提供下一地址生成的灵活的定序器。定序器包括用于接收外部提供的基地址和外部提供的地址偏移值的装置，用于存储返回基地址指针的堆栈，以及用于存储当前程序指针计数器地址的装置。定序器包括用于从多个生成的地址中的一个地址中选择一个地址并在所述微程序的执行中提供所选择的地址作为下一地址的装置，以及用于产生所述多个地址的装置，所述多个地址包括从所述组中选择的地址生成装置包括用于将地址偏移值与堆栈存储的返回基地址相加的装置，用于将地址偏移值与当前节目指针计数器地址相加的装置，用于通过多个预定积分值之一选择性地增加所选择的地址的装置，以及用于选择性地移动所述地址偏移值并且用所述移位的地址偏移值覆盖所述外部基地址的装置，每个装置分别产生所述多个所生成的地址之一。

3. 发明授权

US5007012A Fly-by data transfer system 失效
标题翻译：飞行数据传输系统
公开(公告)号：US5007012A
公开(公告)日：1991-04-09
申请号：US242744
申请日：1988-09-09
申请人： Vineet Dujari
发明人： Vineet Dujari
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method of transferring data in one access cycle between two devices over a communications bus. Data is read from a predetermined location in the first device. The data is also latched into a temporary register. Data is simultaneously written into a predetermined location of a second device. The read operation of the first device is terminated and the data from the temporary register is applied to the second device simultaneously with the termination step so that data is available to the second device notwithstanding the fact that the first device has ceased transmission.

4. 发明授权

US4618898A Method and apparatus for reading a disk 失效
标题翻译：读取磁盘的方法和装置
公开(公告)号：US4618898A
公开(公告)日：1986-10-21
申请号：US684423
申请日：1984-12-20
申请人： Mark S. Young , John Drew , Michael C. Shebanow , Vineet Dujari
发明人： Mark S. Young , John Drew , Michael C. Shebanow , Vineet Dujari
IPC分类号： G11B5/012 , G11B20/12 , G11B27/30 , G11B5/09
CPC分类号： G11B27/3027 , G11B20/12 , G11B5/012 , G11B2220/20 , G11B2220/2508
摘要： A method and apparatus for reading data from a disk having missing or unreadable field address marks. Expected address marks are searched for within a time window which is generated using a counter. When an expected address mark is generated at any time within the time window, the counter is set or reset to generate another time window within which the next address mark is expected to occur. By starting or restarting the counter each time an expected address mark is detected the effects of variations in spindle speed which occur prior to the detection of the address mark are eliminated, thus increasing the probability that readable address marks will be detected within a time window.
摘要翻译：一种用于从具有丢失或不可读字段地址标记的盘读取数据的方法和装置。在使用计数器生成的时间窗内搜索预期地址标记。当在时间窗口内的任何时候产生预期的地址标记时，计数器被设置或复位以产生预期在其中发生下一个地址标记的另一个时间窗口。每当检测到预期地址标记时，启动或重启计数器，消除了在检测到地址标记之前出现的主轴转速变化的影响，从而增加了在时间窗口内检测可读地址标记的概率。

5. 发明授权

US07475173B2 Integrated disc drive controller 有权
标题翻译：集成磁盘驱动器控制器
公开(公告)号：US07475173B2
公开(公告)日：2009-01-06
申请号：US11378456
申请日：2006-03-17
申请人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
发明人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
IPC分类号： G06F13/00
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0673 , G06F3/0676 , G11B19/00 , G11B20/10009 , G11B25/043
摘要： An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.
摘要翻译：集成数据存储控制系统在单一集成电路中提供RDC，伺服逻辑，ATA接口，微处理器以及其它以前分立的组件，在一个高度集成的系统设计中。使用针对所有组件的单个集成电路技术类型（例如，数字CMOS）来呈现集成电路。模拟和数字电路的组合方式是消除或减少模拟电路组件在数字电路中的噪声或干扰。单个元件可以将它们的输出和输入多路复用在一起，使得各个元件可以选择性地切换（在测试模式期间），使得集成电路以与现有技术组件中的一个相同或相似的方式进行仿真或表现。本发明可以应用于磁性硬盘驱动器（HDD）或诸如软盘控制器，光盘驱动器（例如CD-ROM等），磁带驱动器和其他数据存储设备的其它类型的存储设备。

6. 发明申请

US20060010271A1 Mixed-signal single-chip integrated system electronics for data storage devices 有权
公开(公告)号：US20060010271A1
公开(公告)日：2006-01-12
申请号：US11208348
申请日：2005-08-18
申请人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William Foland , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
发明人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William Foland , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
IPC分类号： G06F13/12
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0673 , G06F3/0676 , G11B19/00 , G11B20/10009 , G11B25/043
摘要： An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.

7. 发明授权

US5239636A Buffer memory subsystem for peripheral controllers 失效
标题翻译：用于外围控制器的缓冲存储器子系统
公开(公告)号：US5239636A
公开(公告)日：1993-08-24
申请号：US242743
申请日：1988-09-09
申请人： Vineet Dujari , Nicos Syrimis
发明人： Vineet Dujari , Nicos Syrimis
IPC分类号： G06F3/06 , G06F13/12
CPC分类号： G06F3/0601 , G06F13/122 , G06F2003/0691
摘要： A buffer memory subsystem for a peripheral controller. A CPU is provided for initiating data transfer. A host adapter is also provided. A memory buffer is used to store data temporarily. The peripheral controller is adapted for operating in an environment having at least two data communications buses: a CPU data communications bus connected between the CPU and the peripheral controller, and a buffer data communications bus, isolated from the CPU data communications bus, and connected to the peripheral controller, to the memory buffer and to the host adapter. In this way, a mechanism is provided to allow the CPU to access the memory buffer by means of the peripheral controller.

8. 发明授权

US5038275A Status transfer structure within a data processing system with status read indication 失效
标题翻译：具有状态读取指示的数据处理系统内的状态转移结构
公开(公告)号：US5038275A
公开(公告)日：1991-08-06
申请号：US475514
申请日：1990-03-02
申请人： Vineet Dujari
发明人： Vineet Dujari
IPC分类号： G06F13/12
CPC分类号： G06F13/126
摘要： A system for transferring the status information between a peripheral controller and central processing unit (CPU) is disclosed. The system utilizes three registers and an interrupt pin for determination of the presence of a STATUS VALID bit. If the STATUS VALID bit is set, then a STATUS OVERFLOW bit is set by the peripheral controller. If the STATUS VALID bit is not set, the peripheral controller updates the status information and sets the STATUS VALID bit. Through the use of this transfer system much of the complexity associated with known systems is eliminated without the concomitant loss in processing speed.
摘要翻译：公开了一种用于在外围控制器和中央处理单元（CPU）之间传送状态信息的系统。该系统使用三个寄存器和一个中断引脚来确定状态有效位的存在。如果STATUS VALID位置1，则外部控制器设置STATUS OVERFLOW位。如果状态有效位未设置，外设控制器将更新状态信息并设置状态有效位。通过使用这种传输系统，消除了与已知系统相关联的许多复杂性，而没有伴随处理速度的损失。

9. 发明授权

US06594716B2 Mixed-signal single-chip integrated system electronics for data storage devices 有权
公开(公告)号：US06594716B2
公开(公告)日：2003-07-15
申请号：US09892489
申请日：2001-06-28
申请人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
发明人： Siamack Nemazie , Kaushik Popat , Balaji Virajpet , William R. Foland, Jr. , Roger McPherson , Maoxin Wei , Vineet Dujari , Shiang-Jyh Chang
IPC分类号： G06F1312
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0673 , G06F3/0676 , G11B19/00 , G11B20/10009 , G11B25/043
摘要： An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.

10. 发明授权

US5537421A Single chip error processor 失效
标题翻译：单芯片错误处理器
公开(公告)号：US5537421A
公开(公告)日：1996-07-16
申请号：US255016
申请日：1988-10-07
申请人： Vineet Dujari , Larry A. Copp
发明人： Vineet Dujari , Larry A. Copp
IPC分类号： G06F11/10 , G06F11/267 , H03M13/15 , G11B20/18
CPC分类号： G06F11/10 , H03M13/15 , G06F11/267
摘要： An error processor on a single integrated circuit chip to detect and correct errors in a block of received data. The error processor includes processing hardware for receiving data and for generating syndrome bytes corresponding to the received data. It also includes processing hardware for detecting errors in the received data and for generating correction vectors to indicate the relative locations and error values thereof. An interface is connected to the processing hardware for facilitating data transfer to and from a communications bus.
摘要翻译：单个集成电路芯片上的错误处理器，用于检测和纠正接收数据块中的错误。误差处理器包括用于接收数据的处理硬件和用于产生对应于接收到的数据的校正子字节。它还包括用于检测接收到的数据中的错误的处理硬件，以及用于产生校正向量以指示其相对位置和误差值。接口连接到处理硬件，以方便数据传输到通信总线和从通信总线传输数据。

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