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1. 发明申请

US20150095677A1 TECHNIQUES FOR PUTTING PLATFORM SUBSYSTEMS INTO A LOWER POWER STATE IN PARALLEL 有权
标题翻译：将平台子系统并入更低功率状态的技术
公开(公告)号：US20150095677A1
公开(公告)日：2015-04-02
申请号：US14040156
申请日：2013-09-27
申请人： VASUDEV BIBIKAR , RAJITH K. MAVILA
发明人： VASUDEV BIBIKAR , RAJITH K. MAVILA
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171 , Y02D50/20
摘要： Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.
摘要翻译：各种实施例通常涉及用于确定具有用于进入较低功率状态的相关联的子系统睡眠控制寄存器的多个子系统中的每一个的睡眠配置状态的装置，方法和其他技术，配置每个相关联的子系统睡眠控制寄存器具有每个子系统的睡眠配置状态，并且当转换到较低功率状态时并行地启用每个子系统的睡眠配置状态。

2. 发明申请

US20060200684A1 Power mode change voltage control in computerized system 审中-公开
标题翻译：电源模式改变电脑系统的电压控制
公开(公告)号：US20060200684A1
公开(公告)日：2006-09-07
申请号：US11069924
申请日：2005-03-01
申请人： Vasudev Bibikar , Rajith Mavila
发明人： Vasudev Bibikar , Rajith Mavila
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A computerized system includes at least one digital logic circuit and a power control circuit. The power control circuit is operable to reduce the voltage of a power signal applied to the at least one digital logic circuit, operable to bring the digital logic circuit from a high power level to a low power level, and operable to increase the voltage of the power signal applied to the digital logic circuit before bringing the digital logic circuit from a low power level to a high power level.
摘要翻译：计算机化系统包括至少一个数字逻辑电路和功率控制电路。功率控制电路可操作以减少施加到至少一个数字逻辑电路的功率信号的电压，可操作以将数字逻辑电路从高功率电平提供到低功率电平，并且可操作以增加将数字逻辑电路从低功率电平提供到高功率电平之前施加到数字逻辑电路的功率信号。

3. 发明申请

US20050289393A1 Power fault handling method, apparatus, and system 有权
标题翻译：电源故障处理方法，装置和系统
公开(公告)号：US20050289393A1
公开(公告)日：2005-12-29
申请号：US10879515
申请日：2004-06-29
申请人： Vasudev Bibikar , Mark Fullerton
发明人： Vasudev Bibikar , Mark Fullerton
IPC分类号： G06F1/30 , G06F1/32 , G06F11/00
CPC分类号： G06F1/30 , G06F1/3203 , G06F11/0721 , G06F11/0772
摘要： A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.
摘要翻译：处理器可以接收对应于潜在电力故障的多个信号。处理器中的控制寄存器可以指定针对每个潜在电力故障采取的动作。

4. 发明申请

US20160021143A1 DEVICE FEDERATION 审中-公开
标题翻译：设备联盟
公开(公告)号：US20160021143A1
公开(公告)日：2016-01-21
申请号：US14336044
申请日：2014-07-21
申请人： DAVID BROWNING , KRISTOFFER FLEMING , VASUDEV BIBIKAR
发明人： DAVID BROWNING , KRISTOFFER FLEMING , VASUDEV BIBIKAR
IPC分类号： H04L29/06
CPC分类号： H04L63/20 , H04L63/104 , H04L63/105
摘要： The present application is directed to device federation. Interaction between devices in a federation may be conducted using reduced security, while interactions with devices outside the federation may be conducted with a variable security up to a standard level of security that may be associated with a communication protocol. A device may comprise at least a communication module and a federation module. The federation module may include at least a relationship rules module having at least one rule based on relationships between devices and a link security control module to control the amount of security utilized during interaction based on the at least one rule. The link security control module may also control how a device may be inducted into a federation by, if necessary, providing qualification data to qualify the device for induction.
摘要翻译：本申请涉及设备联合。可以使用降低的安全性来进行联盟中的设备之间的相互作用，而与联盟之外的设备的交互可以以可变安全性进行，直到可以与通信协议相关联的标准安全级别。设备可以包括至少一个通信模块和联合模块。联合模块可以至少包括关系规则模块，其具有基于设备之间的关系的至少一个规则和链路安全控制模块，以基于至少一个规则来控制在交互期间所利用的安全性的量。链路安全控制模块还可以通过（如果需要）控制设备如何被引入到联盟中，以提供鉴定数据来限定设备的归纳。

5. 发明授权

US07603575B2 Frequency-dependent voltage control in digital logic 有权
标题翻译：数字逻辑中的频率依赖电压控制
公开(公告)号：US07603575B2
公开(公告)日：2009-10-13
申请号：US11173218
申请日：2005-06-30
申请人： Nancy G. Woodbridge , Mark N. Fullerton , Amit Dor , Vasudev Bibikar , Rajith Mavila
发明人： Nancy G. Woodbridge , Mark N. Fullerton , Amit Dor , Vasudev Bibikar , Rajith Mavila
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.
摘要翻译：电子电路包括至少一个数字逻辑电路; 和电源控制电路。功率控制电路可操作以响应于提供给至少一个数字逻辑电路的时钟频率的变化来调节提供给至少一个数字逻辑电路的功率信号的电压。在另一实施例中，功率控制器可操作以在频率增加之前增加施加到数字逻辑电路的功率信号的电压，并且可操作地降低施加到数字逻辑电路之后的功率信号的电压频率下降。

6. 发明申请

US20060005060A1 Power supply detection method, apparatus, and system 有权
标题翻译：电源检测方法，装置和系统
公开(公告)号：US20060005060A1
公开(公告)日：2006-01-05
申请号：US10880762
申请日：2004-06-30
申请人： Vasudev Bibikar , Mark Fullerton , James Feddeler
发明人： Vasudev Bibikar , Mark Fullerton , James Feddeler
IPC分类号： G06F1/26
CPC分类号： G06F1/28 , G06F1/26
摘要： Circuits in a processor may provide an indication that power supplies are ready when waking from a reduced power state. The processor may include timers to measure a period of time, and may utilize voltage detectors to detect the voltages on the power supplies. A control register in the processor may influence the operation.
摘要翻译：处理器中的电路可以提供当从降低功率状态唤醒时电源准备就绪的指示。处理器可以包括测量一段时间的定时器，并且可以使用电压检测器来检测电源上的电压。处理器中的控制寄存器可能会影响操作。

7. 发明申请

US20160091957A1 POWER MANAGEMENT FOR MEMORY ACCESSES IN A SYSTEM-ON-CHIP 审中-公开
标题翻译：系统中的存储器访问的电源管理
公开(公告)号：US20160091957A1
公开(公告)日：2016-03-31
申请号：US14498516
申请日：2014-09-26
申请人： Suketu R. Partiwala , Vasudev Bibikar , Stefan Macher , Verma R. Rohit , Philip Abraham , Irwin J. Vaz , Manan Kathuria
发明人： Suketu R. Partiwala , Vasudev Bibikar , Stefan Macher , Verma R. Rohit , Philip Abraham , Irwin J. Vaz , Manan Kathuria
IPC分类号： G06F1/32 , G11C7/10
CPC分类号： G06F1/3275 , G06F1/3243 , G06F1/3287 , G11C7/1072 , Y02D10/13 , Y02D10/14 , Y02D10/171
摘要： Techniques and mechanisms to manage power states for a system-on-chip (SOC). Multiple modules of the SOC include a first module to perform a task including one or more accesses to a memory. In an embodiment, the SOC is transitioned to one of a path-to-memory-available (PMA) power state and a path-to-memory-not-available (PMNA) power state, where the transition is in response to an indication that, of the multiple modules, only the first module is to access the memory during the task. The PMA power state enables data communication between the memory and the first module and prevents data communication between the memory and any other module of the multiple modules. In another embodiment, the PMNA power state prevents data communication between the memory and any of the multiple modules, but allows a low latency transition from the PMNA power state to the PMA power state.
摘要翻译：用于管理片上系统（SOC）的电源状态的技术和机制。 SOC的多个模块包括执行包括对存储器的一个或多个访问的任务的第一模块。在一个实施例中，SOC被转换到路径到存储器可用（PMA）功率状态和路径到存储器不可用（PMNA）功率状态之一，其中转换响应于指示在多个模块中，只有第一个模块才能在任务期间访问内存。 PMA电源状态使得存储器和第一模块之间的数据通信能够防止存储器与多个模块的任何其他模块之间的数据通信。在另一个实施例中，PMNA功率状态防止存储器与多个模块中的任何一个之间的数据通信，但允许从PMNA功率状态到PMA功率状态的低延迟转换。

8. 发明申请

US20070006007A1 Frequency-dependent voltage control in digital logic 有权
标题翻译：数字逻辑中的频率依赖电压控制
公开(公告)号：US20070006007A1
公开(公告)日：2007-01-04
申请号：US11173218
申请日：2005-06-30
申请人： Nancy Woodbridge , Mark Fullerton , Amit Dor , Vasudev Bibikar , Rajith Mavila
发明人： Nancy Woodbridge , Mark Fullerton , Amit Dor , Vasudev Bibikar , Rajith Mavila
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.
摘要翻译：电子电路包括至少一个数字逻辑电路; 和电源控制电路。功率控制电路可操作以响应于提供给至少一个数字逻辑电路的时钟频率的变化来调节提供给至少一个数字逻辑电路的功率信号的电压。在另一实施例中，功率控制器可操作以在频率增加之前增加施加到数字逻辑电路的功率信号的电压，并且可操作地降低施加到数字逻辑电路之后的功率信号的电压频率下降。

9. 发明申请

US20160018462A1 APPARATUS AND METHOD TO DEBUG A VOLTAGE REGULATOR 有权
标题翻译：调试电压调节器的装置和方法
公开(公告)号：US20160018462A1
公开(公告)日：2016-01-21
申请号：US14335066
申请日：2014-07-18
申请人： SANKARAN MENON , VASUDEV BIBIKAR , SAHAJANANDA REDDY P , SUNGHYUN KOH , NAVEENDRAN BALASINGAM
发明人： SANKARAN MENON , VASUDEV BIBIKAR , SAHAJANANDA REDDY P , SUNGHYUN KOH , NAVEENDRAN BALASINGAM
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/31725 , G01R31/025 , G01R31/40 , G05F1/10
摘要： Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.
摘要翻译：描述了一种装置，包括：具有参考输入节点的第一电压调节器（VR）; 以及第一多路复用器，用于向参考输入节点提供参考电压并且可操作以选择至少两个不同参考电压中的一个作为参考电压。

10. 发明申请

US20150381227A1 INTERNET OF THINGS ELECTRONIC SIGNAL AGGREGATOR AND REPEATER 有权
标题翻译：电子信号聚合器和重复器的互联网
公开(公告)号：US20150381227A1
公开(公告)日：2015-12-31
申请号：US14450482
申请日：2014-08-04
申请人： David W. Browning , Kristoffer D. Fleming , Robert E. Gough , Guy G. Sotomayor , Vasudev Bibikar , Ankush Varma
发明人： David W. Browning , Kristoffer D. Fleming , Robert E. Gough , Guy G. Sotomayor , Vasudev Bibikar , Ankush Varma
IPC分类号： H04B1/40 , H04W4/00
CPC分类号： H04W4/70 , H04W84/20
摘要： The present disclosure is directed to logging random “chirps” of IoT devices and rebroadcasting these chirps to other devices on demand. An apparatus consistent with the present disclosure includes a transmitter to communicate with a network of wireless-communication-enabled devices. The apparatus also includes a receiver to detect communications transmitted from the wireless-communication-enabled device. Further, the apparatus includes control unit logic to tally the number of electrical signals emitted from each wireless-communication-enabled device. In addition, the apparatus includes memory to store the number of emitted electrical signals. The apparatus further includes a power unit electrically coupled to the transmitter, receiver, and memory.
摘要翻译：本公开旨在记录IoT设备的随机“啁啾”，并根据需要将这些啁啾转播给其他设备。与本公开一致的装置包括与无线通信使能设备的网络进行通信的发射机。该装置还包括用于检测从启用无线通信的设备发送的通信的接收机。此外，该装置包括控制单元逻辑，用于计数从每个启用无线通信的设备发射的电信号的数量。此外，该装置包括用于存储所发射的电信号的数量的存储器。该装置还包括电耦合到发射器，接收器和存储器的功率单元。

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