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1. 发明申请

US20120320695A1 Pre-Charge Voltage Generation and Power Saving Modes 有权
标题翻译：预充电电压产生和省电模式
公开(公告)号：US20120320695A1
公开(公告)日：2012-12-20
申请号：US13599836
申请日：2012-08-30
申请人： Valerie L. Lines , HakJune OH
发明人： Valerie L. Lines , HakJune OH
IPC分类号： G11C7/00
CPC分类号： G11C5/148 , G11C5/147 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C2207/2227
摘要： A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.
摘要翻译：系统包括电压发生器，以产生用于对存储器电路中的一个或多个信号进行预充电的预充电电压信号。一个或多个信号可以是用于访问存储器的数据总线。电压发生器可以包括指示存储器电路是否被设置为省电模式的输入。根据一个实施例，输入调节由电压发生器产生的预充电电压信号的幅度。这种实施例对于常规方法是有用的，因为调节预充电电压可导致功率节省。例如，在省电模式下，电压发生器电路可以将预充电电压调整为减小与预充电电压相关联的漏电流量的值。减少相对于预充电电压的泄漏意味着所节省的功率可以用于其他有用的目的。

2. 发明授权

US08023314B2 Dynamic memory word line driver scheme 失效
标题翻译：动态内存字线驱动方案
公开(公告)号：US08023314B2
公开(公告)日：2011-09-20
申请号：US12405153
申请日：2009-03-16
申请人： Valerie L. Lines
发明人： Valerie L. Lines
IPC分类号： G11C11/24
CPC分类号： G11C8/08 , G11C11/4085
摘要： A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines whereby an above Vdd voltage level word line is achieved without the use of double boot-strap circuits.
摘要翻译：准确地将字线（传输晶体管栅极）驱动电压控制到电压的电路，该电压被控制并且不显着大于驱动字线所需的电压。该电路消除了双引导电路的需要，并确保没有电压超过完全打开存储单元存取晶体管所需的电压。避免超过降低可靠性的电压，并获得精确的驱动电压。 DRAM包括字线，具有连接到字线的使能输入的存储器单元，栅极接收字线以第一逻辑电平Vss和Vdd选择信号，以及用于提供电平Vss和Vdd的选择信号，高电压源Vpp 其电压高于Vdd，用于将电平Vss和Vdd的选择信号转换为电平Vss和Vpp并用于将其直接应用于字线的电路，从而实现上述Vdd电压电平字线而不使用双引导 - 电路。

3. 发明申请

US20110122719A1 PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES 有权
标题翻译：预充电电压和节电模式
公开(公告)号：US20110122719A1
公开(公告)日：2011-05-26
申请号：US13019100
申请日：2011-02-01
申请人： Valerie L. Lines , HakJune Oh
发明人： Valerie L. Lines , HakJune Oh
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C5/147 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C2207/2227
摘要： A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.
摘要翻译：系统包括电压发生器，以产生用于对存储器电路中的一个或多个信号进行预充电的预充电电压信号。一个或多个信号可以是用于访问存储器的数据总线。电压发生器可以包括指示存储器电路是否被设置为省电模式的输入。根据一个实施例，输入调节由电压发生器产生的预充电电压信号的幅度。这种实施例对于常规方法是有用的，因为调节预充电电压可导致功率节省。例如，在省电模式下，电压发生器电路可以将预充电电压调整为减小与预充电电压相关联的漏电流量的值。减少相对于预充电电压的泄漏意味着所节省的功率可以用于其他有用的目的。

4. 发明授权

US06236581B1 High voltage boosted word line supply charge pump and regulator for DRAM 失效
标题翻译：高压升压字线供电电荷泵和稳压器用于DRAM
公开(公告)号：US06236581B1
公开(公告)日：2001-05-22
申请号：US09483626
申请日：2000-01-14
申请人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
发明人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
IPC分类号： H02M318
CPC分类号： G11C5/145 , G05F3/205 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , H02M3/07
摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by Vtn as in the prior art. The boosting capacitors are charged by Vdd, thus eliminating drift tracking problems associated with clock boosting sources and Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
摘要翻译：用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。升压电路中的晶体管完全切换，消除了如现有技术中Vtn的升压电压的降低。升压电容由Vdd充电，从而消除与时钟增压源和Vdd相关的漂移跟踪问题。调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

5. 发明授权

US6061277A Dynamic memory word line driver scheme 失效
公开(公告)号：US6061277A
公开(公告)日：2000-05-09
申请号：US123112
申请日：1998-07-27
申请人： Valerie L. Lines
发明人： Valerie L. Lines
IPC分类号： G11C11/407 , G11C8/08 , G11C11/408 , G11C16/04
CPC分类号： G11C11/4085 , G11C8/08
摘要： A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM is comprised of word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels V.sub.ss and V.sub.dd, and for providing a select signal at levels V.sub.ss and V.sub.dd, a high voltage supply source V.sub.pp which is higher in voltage than V.sub.dd, a circuit for translating the select signals at levels V.sub.ss and V.sub.dd to levels V.sub.ss and V.sub.pp and for applying it directly to the word lines for application to the enable inputs whereby an above V.sub.dd voltage level word line is achieved without the use of double boot-strap circuits.

6. 发明授权

US5828620A High voltage boosted word line supply charge pump and regulator for DRAM 失效
公开(公告)号：US5828620A
公开(公告)日：1998-10-27
申请号：US921579
申请日：1997-09-02
申请人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
发明人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
IPC分类号： G05F3/20 , G11C5/14 , G11C8/08 , G11C11/4074 , G11C11/408 , H02M3/07 , G11C7/00
CPC分类号： G11C5/145 , G05F3/205 , G11C11/4074 , G11C11/4085 , G11C5/147 , G11C8/08 , H02M3/07
摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

7. 发明授权

US5699313A High voltage boosted word line supply charge pump and regulator for dram 失效
标题翻译：高压提升字线供电电荷泵和稳压器
公开(公告)号：US5699313A
公开(公告)日：1997-12-16
申请号：US684252
申请日：1996-07-19
申请人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
发明人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
IPC分类号： G05F3/20 , G11C5/14 , G11C8/08 , G11C11/4074 , G11C11/408 , H02M3/07 , G11C13/00
CPC分类号： G11C5/145 , G05F3/205 , G11C11/4074 , G11C11/4085 , G11C5/147 , G11C8/08 , H02M3/07
摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
摘要翻译：用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。升压电路中的晶体管完全切换，消除了如现有技术中Vtn的升压电压的降低。升压电容由Vdd充电，从而消除与时钟增压源和Vdd相关的漂移跟踪问题。调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

8. 发明授权

US5406523A High voltage boosted word line supply charge pump and regulator for DRAM 失效
标题翻译：高压升压字线供电电荷泵和稳压器用于DRAM
公开(公告)号：US5406523A
公开(公告)日：1995-04-11
申请号：US134621
申请日：1993-10-12
申请人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
发明人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
IPC分类号： G11C11/407 , G05F3/20 , G11C5/14 , G11C8/08 , G11C11/4074 , G11C11/408 , H02M3/07 , G11C13/00
CPC分类号： G05F3/205 , G11C11/4074 , G11C11/4085 , G11C5/145 , G11C5/147 , G11C8/08 , H02M3/07
摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating draft tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
摘要翻译：用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。升压电路中的晶体管完全切换，消除了如现有技术中Vtn的升压电压的降低。升压电容器由Vdd充电，从而消除与时钟增压源和Vdd相关的牵引跟踪问题。调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

9. 发明授权

US5267201A High voltage boosted word line supply charge pump regulator for DRAM 失效
标题翻译：用于DRAM的高压升压字线供电电荷泵稳压器
公开(公告)号：US5267201A
公开(公告)日：1993-11-30
申请号：US680994
申请日：1991-04-05
申请人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
发明人： Richard C. Foss , Peter B. Gillingham , Robert F. Harland , Valerie L. Lines
IPC分类号： G11C11/407 , G05F3/20 , G11C5/14 , G11C8/08 , G11C11/4074 , G11C11/408 , H02M3/07 , G11C7/00
CPC分类号： G05F3/205 , G11C11/4074 , G11C11/4085 , G11C5/145 , G11C5/147 , G11C8/08 , H02M3/07
摘要： A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating drift tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
摘要翻译：用于提供用于DRAM字线的输出电压的电路，其可用于驱动可高达2Vdd的存储器字线。升压电路中的晶体管完全切换，消除了如现有技术中Vtn的升压电压的降低。升压电容由Vdd充电，从而消除与时钟增压源和Vdd相关的漂移跟踪问题。调节器检测存储单元存取晶体管的复制品的传导电流，当达到操作存取晶体管的正确电压时，切断升压电路时钟振荡器。

10. 发明授权

US5245576A Dynamic memory row/column redundancy scheme 失效
标题翻译：动态记忆OW / /。。。。。。。
公开(公告)号：US5245576A
公开(公告)日：1993-09-14
申请号：US680995
申请日：1991-04-05
申请人： Richard C. Foss , Valerie L. Lines , Akira Yoneyama
发明人： Richard C. Foss , Valerie L. Lines , Akira Yoneyama
IPC分类号： G11C29/00
CPC分类号： G11C29/787 , G11C29/84
摘要： A DRAM row or column decoder having a fused stage for disabling defective rows or columns. A fuse is placed within a stage preceding the final output stage of a multi-stage row or column decoder. Because the fuse is not placed within the output stage, it is not necessary to have one fuse for each individual row or column; a single fuse can disable several decoder outputs, and thus several rows or columns can be disabled at the same time.
摘要翻译：具有用于禁止有缺陷的行或列的熔化级的DRAM行或列解码器。保险丝放置在多级行或列解码器的最终输出级之前的级内。由于保险丝未放置在输出级内，因此不需要为每个单独的行或列设置一个保险丝; 单个保险丝可以禁用多个解码器输出，因此可以同时禁用多个行或列。

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