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1. 发明申请

WO2012125310A1 SYSTEM AND METHOD OF UPDATING DRIVE SCHEME VOLTAGES 审中-公开
标题翻译：更新驱动方案电压的系统和方法
公开(公告)号：WO2012125310A1
公开(公告)日：2012-09-20
申请号：PCT/US2012/027559
申请日：2012-03-02
申请人： QUALCOMM MEMS TECHNOLOGIES, INC. , CHEUI, Nao S. , AFLATOONI, Koorosh , VAN LIER, Wilhelmus Johannes Robertus , VARMA, Pramod K. , GOEL, Ramesh K. , VENUGOPAL, Sameer
发明人： CHEUI, Nao S. , AFLATOONI, Koorosh , VAN LIER, Wilhelmus Johannes Robertus , VARMA, Pramod K. , GOEL, Ramesh K. , VENUGOPAL, Sameer
IPC分类号： G09G3/34 , G09G3/36
CPC分类号： G09G3/3466 , G09G3/3433 , G09G3/3629 , G09G3/3651 , G09G2320/0693
摘要： This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for calibrating display arrays. In one aspect, a method of calibrating a display array includes determining a particular drive response characteristic and updating a particular drive scheme voltage between updates of image data on the display array.
摘要翻译：本公开提供了用于校准显示器阵列的系统，方法和装置，包括编码在计算机存储介质上的计算机程序。在一个方面，校准显示器阵列的方法包括确定特定驱动器响应特性并且在显示器阵列上的图像数据的更新之间更新特定驱动器方案电压。

2. 发明申请

WO2010123619A2 METHODS AND SYSTEM FOR ON-CHIP DECODER FOR ARRAY TEST 审中-公开
标题翻译：用于阵列测试的片上解码器的方法和系统
公开(公告)号：WO2010123619A2
公开(公告)日：2010-10-28
申请号：PCT/US2010/024990
申请日：2010-02-23
申请人： ARIZONA BOARD OF REGENTS, A BODY CORPORATE ACTING FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , BAWOLEK, Edward, J. , MOYER, Curtis, D. , VENUGOPAL, Sameer, M.
发明人： BAWOLEK, Edward, J. , MOYER, Curtis, D. , VENUGOPAL, Sameer, M.
IPC分类号： G09G3/00
CPC分类号： H01L22/00 , G09G3/006 , G09G2320/0295 , G09G2330/04 , G09G2330/10 , G09G2330/12 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides devices capable of testing the electrical performance of thin- film transistor backplane arrays and methods for their use.
摘要翻译：本发明提供能够测试薄膜晶体管背板阵列的电气性能的装置及其使用方法。

3. 发明申请

WO2010123619A3 METHODS AND SYSTEM FOR ON-CHIP DECODER FOR ARRAY TEST 审中-公开
标题翻译：用于阵列测试的片上解码器的方法和系统
公开(公告)号：WO2010123619A3
公开(公告)日：2011-02-24
申请号：PCT/US2010024990
申请日：2010-02-23
申请人： UNIV ARIZONA , BAWOLEK EDWARD J , MOYER CURTIS D , VENUGOPAL SAMEER M
发明人： BAWOLEK EDWARD J , MOYER CURTIS D , VENUGOPAL SAMEER M
IPC分类号： G09G3/00
CPC分类号： H01L22/00 , G09G3/006 , G09G2320/0295 , G09G2330/04 , G09G2330/10 , G09G2330/12 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides devices capable of testing the electrical performance of thin- film transistor backplane arrays and methods for their use.
摘要翻译：本发明提供能够测试薄膜晶体管背板阵列的电气性能的装置及其使用方法。

4. 发明申请

WO2010123620A1 METHODS AND SYSTEM FOR ELECTROSTATIC DISCHARGE PROTECTION OF THIN-FILM TRANSISTOR BACKPLANE ARRAYS 审中-公开
标题翻译：薄膜晶体管背板阵列静电放电保护方法与系统
公开(公告)号：WO2010123620A1
公开(公告)日：2010-10-28
申请号：PCT/US2010/025043
申请日：2010-02-23
申请人： ARIZONA BOARD OF REGENTS, A BODY CORPORATE ACTING FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , BAWOLEK, Edward, J. , MOYER, Curtis, D. , VENUGOPAL, Sameer, M.
发明人： BAWOLEK, Edward, J. , MOYER, Curtis, D. , VENUGOPAL, Sameer, M.
IPC分类号： G09G3/00
CPC分类号： G09G3/006 , G01R31/26 , G01R31/2607 , G01R31/2621 , G01R31/2642 , G09G2320/0295 , G09G2330/04 , G09G2330/10 , G09G2330/12 , Y10T29/49169
摘要： The present invention provides devices and methods for testing the electrical performance of thin- film transistor backplane arrays and protecting thin- films during testing and handling.
摘要翻译：本发明提供用于测试薄膜晶体管背板阵列的电气性能并在测试和处理期间保护薄膜的装置和方法。

5. 发明申请

WO2010042820A1 DIFFERENTIAL THRESHOLD VOLTAGE NON-VOLATILE MEMORY AND RELATED METHODS 审中-公开
标题翻译：差分门限电压非易失性存储器及相关方法
公开(公告)号：WO2010042820A1
公开(公告)日：2010-04-15
申请号：PCT/US2009/060171
申请日：2009-10-09
申请人： ARIZONA BOARD OF REGENTS, FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , VENUGOPAL, Sameer , ALLEE, David, R. , CLARK, Lawrence, T.
发明人： VENUGOPAL, Sameer , ALLEE, David, R. , CLARK, Lawrence, T.
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/26 , Y10T29/49117
摘要： Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related method are also disclosed herein.
摘要翻译：本文描述了差分阈值电压非易失性存储器及相关方法的实施例和示例。本文还公开了其它实施例，其示例和相关方法。

6. 发明申请

WO2011084229A3 EMBEDDED MEMS SENSORS AND RELATED METHODS 审中-公开
标题翻译：嵌入式MEMS传感器及相关方法
公开(公告)号：WO2011084229A3
公开(公告)日：2011-11-10
申请号：PCT/US2010055688
申请日：2010-11-05
申请人： UNIV ARIZONA , LAKAMRAJU NARENDRA V , VENUGOPAL SAMEER M
发明人： LAKAMRAJU NARENDRA V , VENUGOPAL SAMEER M
IPC分类号： B81C1/00 , B81B7/02 , H01L21/64
CPC分类号： B81C1/00246 , B81B2201/0235 , B81C2203/0742 , G01L9/005 , G01L9/0073
摘要： Embodiments of embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein.
摘要翻译：这里描述了嵌入式MEMS传感器和相关方法的实施例。本文还公开了其他实施例和相关方法。

7. 发明申请

WO2011084229A2 EMBEDDED MEMS SENSORS AND RELATED METHODS 审中-公开
标题翻译：嵌入式MEMS传感器及相关方法
公开(公告)号：WO2011084229A2
公开(公告)日：2011-07-14
申请号：PCT/US2010/055688
申请日：2010-11-05
申请人： ARIZONA BOARD OF REGENTS, FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , LAKAMRAJU, Narendra, V. , VENUGOPAL, Sameer, M.
发明人： LAKAMRAJU, Narendra, V. , VENUGOPAL, Sameer, M.
IPC分类号： B81C1/00 , B81B7/02 , H01L21/64
CPC分类号： B81C1/00246 , B81B2201/0235 , B81C2203/0742 , G01L9/005 , G01L9/0073
摘要： Embodiments of embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein.
摘要翻译：本文描述了嵌入式MEMS传感器和相关方法的实施例。本文还公开了其它实施例和相关方法。

8. 发明申请

WO2011071573A3 AMPLIFIERS WITH DEPLETION AND ENHANCEMENT MODE THIN FILM TRANSISTORS AND RELATED METHODS 审中-公开
公开(公告)号：WO2011071573A3
公开(公告)日：2011-06-16
申请号：PCT/US2010/047336
申请日：2010-08-31
申请人： ARIZONA BOARD OF REGENTS, FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , VENUGOPAL, Sameer, M. , DEY, Aritra , ALLEE, David, R.
发明人： VENUGOPAL, Sameer, M. , DEY, Aritra , ALLEE, David, R.
IPC分类号： H03F1/22 , H03F3/16
摘要： In one embodiment, an apparatus comprises an integrated circuit comprising an amplifier. The amplifier can comprise a first transistor over a substrate of the integrated circuit, and a second transistor over the substrate and coupled to the first transistor. The first transistor can comprise a first source terminal, a first drain terminal, and a first gate terminal. The second transistor can comprise a second source terminal, a second drain terminal, and a second gate terminal. An input node of the amplifier can be coupled to the second transistor, such as to the second gate terminal. An output node of the amplifier can be coupled between the first and second transistors, such as by coupling the second drain terminal and the first source terminal together at the output node. In the same or other embodiments, the first and second transistors comprise thin film transistors, and the substrate comprises a flexible substrate. The first transistor comprises a threshold voltage alterable from an initial threshold voltage value to a target threshold voltage value, and the first gate terminal the first source terminal are configured to be selectively coupled together. Other examples and embodiments are described herein.

9. 发明申请

WO2011071573A2 AMPLIFIERS WITH DEPLETION AND ENHANCEMENT MODE THIN FILM TRANSISTORS AND RELATED METHODS 审中-公开
标题翻译：放大器和增强型薄膜晶体管放大器及相关方法
公开(公告)号：WO2011071573A2
公开(公告)日：2011-06-16
申请号：PCT/US2010047336
申请日：2010-08-31
申请人： UNIV ARIZONA , VENUGOPAL SAMEER M , DEY ARITRA , ALLEE DAVID R
发明人： VENUGOPAL SAMEER M , DEY ARITRA , ALLEE DAVID R
IPC分类号： H03F1/22 , H03F3/16
CPC分类号： H03F3/16 , H03F1/223 , Y10T29/49169
摘要： In one embodiment, an apparatus comprises an integrated circuit comprising an amplifier. The amplifier can comprise a first transistor over a substrate of the integrated circuit, and a second transistor over the substrate and coupled to the first transistor. The first transistor can comprise a first source terminal, a first drain terminal, and a first gate terminal. The second transistor can comprise a second source terminal, a second drain terminal, and a second gate terminal. An input node of the amplifier can be coupled to the second transistor, such as to the second gate terminal. An output node of the amplifier can be coupled between the first and second transistors, such as by coupling the second drain terminal and the first source terminal together at the output node. In the same or other embodiments, the first and second transistors comprise thin film transistors, and the substrate comprises a flexible substrate. The first transistor comprises a threshold voltage alterable from an initial threshold voltage value to a target threshold voltage value, and the first gate terminal the first source terminal are configured to be selectively coupled together. Other examples and embodiments are described herein.
摘要翻译：在一个实施例中，一种装置包括包括放大器的集成电路。放大器可以包括在集成电路的衬底上的第一晶体管，以及位于衬底上并耦合到第一晶体管的第二晶体管。第一晶体管可以包括第一源极端子，第一漏极端子和第一栅极端子。第二晶体管可以包括第二源极端子，第二漏极端子和第二栅极端子。放大器的输入节点可以耦合到第二晶体管，例如耦合到第二栅极端子。放大器的输出节点可以耦合在第一和第二晶体管之间，例如通过在输出节点处将第二漏极端子和第一源极端子耦合在一起。在相同或其它实施例中，第一和第二晶体管包括薄膜晶体管，并且衬底包括柔性衬底。第一晶体管包括可从初始阈值电压值改变到目标阈值电压值的阈值电压，第一栅极端子被配置为选择性地耦合在一起。本文描述了其它示例和实施例。

10. 发明申请

WO2010110827A1 DISPLAYS WITH EMBEDDED MEMS SENSORS AND RELATED METHODS 审中-公开
标题翻译：嵌入式MEMS传感器的展示和相关方法
公开(公告)号：WO2010110827A1
公开(公告)日：2010-09-30
申请号：PCT/US2009/068523
申请日：2009-12-17
申请人： ARIZONA BOARD OF REGENTS, FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , VENUGOPAL, Sameer, M. , LAKAMRAJU, Narendra, V.
发明人： VENUGOPAL, Sameer, M. , LAKAMRAJU, Narendra, V.
IPC分类号： G01M7/00
CPC分类号： G01L19/083 , G06F3/0412 , G06F3/044
摘要： Embodiments of displays with embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein.
摘要翻译：本文描述了具有嵌入式MEMS传感器的显示器和相关方法的实施例。本文还公开了其它实施例和相关方法。

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