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1. 发明申请

WO1994022143A1 MEMORY CELL INSENSITIVE TO HEAVY ION COLLISIONS 审中-公开
标题翻译：记忆细胞对重离子碰撞无效
公开(公告)号：WO1994022143A1
公开(公告)日：1994-09-29
申请号：PCT/FR1994000287
申请日：1994-03-16
申请人： CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE , BESSOT, Denis , VELAZCO, Raoul
发明人： CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
IPC分类号： G11C11/412
CPC分类号： G11C11/4125
摘要： A memory cell comprising two assemblies each including first to third transistors (MP1, MN1, MN5; MP2, MN2, MN6) mounted in series between high (Vdd) and low (Vss) potentials and having p-, n- and n-channels respectively. The gate of one n-channel transistor in each assembly is connected to the output node (Q, Q*) of the other assembly while the gate of the other n-channel transistor in each assembly is connected to the gate of the first transistor in the same assembly. A fourth p-channel transistor (MP3, MP5) combined with each assembly is arranged between the high potential (Vdd) and the gate of the first transistor (MP1, MP2) in the assembly. A fifth p-channel transistor (MP4, MP6) combined with each assembly is arranged between the gate of the first transistor in the assembly and a read/write line (RW) or the low potential (Vss).
摘要翻译：一种存储单元，包括两个组件，每个组件包括串联安装在高（Vdd）和低（Vss）电位之间并且具有p，n和n通道的第一至第三晶体管（MP1，MN1，MN5; MP2，MN2，MN6）分别。每个组件中的一个n沟道晶体管的栅极连接到另一组件的输出节点（Q，Q *），而每个组件中另一个n沟道晶体管的栅极连接到第一晶体管的栅极同一个装配。与组件中的每一组合组合的第四个P沟道晶体管（MP3，MP5）被布置在组件中的高电位（Vdd）和第一晶体管（MP1，MP2）的栅极之间。与组件结合的第五个p沟道晶体管（MP4，MP6）被布置在组件中的第一晶体管的栅极和读/写线（RW）或低电位（Vss）之间。

2. 发明申请

WO1994022144A1 RADIATION-INSENSITIVE MEMORY CELL 审中-公开
标题翻译：辐射敏感记忆体
公开(公告)号：WO1994022144A1
公开(公告)日：1994-09-29
申请号：PCT/FR1994000288
申请日：1994-03-16
申请人： CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE , BESSOT, Denis , VELAZCO, Raoul
发明人： CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
IPC分类号： G11C11/412
CPC分类号： G11C11/4125
摘要： A memory cell comprising two assemblies each including first to third transistors (MP1, MN5, MN1; MP2, MN6, MN2) arranged between high and low potentials (Vdd, Vss). The first transistor (MP1, MP2) is a p-channel transistor while the second and third are n-channel transistors. The gate of the third transistor in each assembly is connected to the output node of the other assembly while the gate of the second transistor in each assembly is connected to the gate of the first transistor in the other assembly. A fourth p-channel transistor (MP3, MP4) combined with each assembly is arranged between the high potential (Vdd) and the gate of the first transistor (MP1, MP2) in the assembly. A fifth n-channel transistor (MN7, MN8) combined with each assembly is arranged between the gate of the first transistor in the assembly and the low potential (Vss).
摘要翻译：一种存储单元，包括两个组件，每个组件包括布置在高电位和低电位（Vdd，Vss）之间的第一至第三晶体管（MP1，MN5，MN1; MP2，MN6，MN2）。第一晶体管（MP1，MP2）是p沟道晶体管，而第二晶体管和第三晶体管是n沟道晶体管。每个组件中的第三晶体管的栅极连接到另一组件的输出节点，而每个组件中的第二晶体管的栅极连接到另一组件中的第一晶体管的栅极。与组件中组合的第四个P沟道晶体管（MP3，MP4）被布置在组件中的高电位（Vdd）和第一晶体管（MP1，MP2）的栅极之间。与组件结合的第五n沟道晶体管（MN7，MN8）被布置在组件中的第一晶体管的栅极和低电位（Vss）之间。

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