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1. 发明申请

WO2013006672A3 PROGRAMMABLE PATCH ARCHITECTURE FOR ROM 审中-公开
标题翻译： ROM的可编程补丁架构
公开(公告)号：WO2013006672A3
公开(公告)日：2013-03-14
申请号：PCT/US2012045501
申请日：2012-07-05
申请人： INTEL CORP , VARMA VISHAL V , KOSHY KAMAL J
发明人： VARMA VISHAL V , KOSHY KAMAL J
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/328
摘要： A system according to one embodiment includes a host central processing unit (CPU); a first storage medium configured to be in communication with the host CPU and to store information associated with at least one address; a second storage medium configured to be in communication with the host CPU, to store patch information associated with the at least one address of the first storage medium; and selection circuitry configured to, in response to a fetch instruction from the host CPU, select the patch information from the second storage medium if the fetch instruction contains a destination address that matches the at least one address associated with the patch information.
摘要翻译：根据一个实施例的系统包括主机中央处理单元（CPU）第一存储介质，被配置为与主机CPU通信并存储与至少一个地址相关联的信息; 第二存储介质，其被配置为与所述主机CPU通信，以存储与所述第一存储介质的所述至少一个地址相关联的补丁信息; 以及选择电路，被配置为响应于来自所述主机CPU的获取指令，如果所述获取指令包含与与所述补丁信息相关联的所述至少一个地址匹配的目的地地址，则从所述第二存储介质选择所述补丁信息。

2. 发明申请

WO2007087636A1 METHODS, DEVICES AND SYSTEMS RELATING TO RESELECTING CELLS IN A CELLULAR WIRELESS COMMUNICATIONS SYSTEM 审中-公开
标题翻译：方法，与蜂窝无线通信系统中的细胞相关的装置和系统
公开(公告)号：WO2007087636A1
公开(公告)日：2007-08-02
申请号：PCT/US2007/061166
申请日：2007-01-26
申请人： QUALCOMM INCORPORATED , TEBBIT, Nicholas John , AGARWAL, Amit , NARANG, Mohit , VARMA, Vishal V.
发明人： TEBBIT, Nicholas John , AGARWAL, Amit , NARANG, Mohit , VARMA, Vishal V.
IPC分类号： H04Q7/38
CPC分类号： H04W36/30
摘要： Cell reselection comprises monitoring a first indicator indicative of a signaling level of the serving cell, and monitoring second indicators, each indicative of a signaling level of one of plural potential target cells. A timer associated with a potential target cell is initiated when the respective second indicator indicates that the signaling level of the potential target cell is better than the signaling level of the serving cell. Each timer has an associated expiry, and, if at least one timer has been initiated by the expiry of another initiated timer, then, after delaying for an additional period after at least the first timer has expired, a target cell is selected from the potential target cells. The target cell is selected that has a second indicator which indicates that the signaling level of the respective target cell is better than the signaling level of the serving cell.
摘要翻译：小区重选包括监视指示服务小区的信令级别的第一指示符，以及监视第二指示符，每个指示符指示多个潜在目标小区之一的信令级别。当相应的第二指示符指示潜在目标小区的信令级别优于服务小区的信令级别时，启动与潜在目标小区相关联的定时器。每个定时器具有相关联的到期，并且如果至少一个定时器已经被另一个发起的定时器的到期启动，则在至少第一定时器到期之后延迟一个额外的时间段之后，从电位中选择一个目标小区靶细胞。选择具有指示相应目标小区的信令级别优于服务小区的信令级别的第二指示符的目标小区。

3. 发明申请

WO2013006672A2 PROGRAMMABLE PATCH ARCHITECTURE FOR ROM 审中-公开
标题翻译： ROM可编程配对架构
公开(公告)号：WO2013006672A2
公开(公告)日：2013-01-10
申请号：PCT/US2012/045501
申请日：2012-07-05
申请人： INTEL CORPORATION , VARMA, Vishal V. , KOSHY, Kamal J.
发明人： VARMA, Vishal V. , KOSHY, Kamal J.
CPC分类号： G06F9/328
摘要： A system according to one embodiment includes a host central processing unit (CPU); a first storage medium configured to be in communication with the host CPU and to store information associated with at least one address; a second storage medium configured to be in communication with the host CPU, to store patch information associated with the at least one address of the first storage medium; and selection circuitry configured to, in response to a fetch instruction from the host CPU, select the patch information from the second storage medium if the fetch instruction contains a destination address that matches the at least one address associated with the patch information.
摘要翻译：根据一个实施例的系统包括主机中央处理单元（CPU）; 配置为与所述主机CPU通信并存储与至少一个地址相关联的信息的第一存储介质; 配置为与所述主机CPU通信的第二存储介质，以存储与所述第一存储介质的所述至少一个地址相关联的补丁信息; 以及选择电路，被配置为响应于来自所述主机CPU的获取指令，如果所述获取指令包含与所述补丁信息相关联的所述至少一个地址匹配的目的地地址，则从所述第二存储介质选择所述补丁信息。

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