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1. 发明申请

WO2003098811A3 MEMORY FOR TURBO DECODER 审中-公开
公开(公告)号：WO2003098811A3
公开(公告)日：2003-11-27
申请号：PCT/IB2003/001911
申请日：2003-05-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , CHARPENTIER, Sebastien , VALDENAIRE, Patrick
发明人： CHARPENTIER, Sebastien , VALDENAIRE, Patrick
IPC分类号： H03M13/29
摘要： The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.

2. 发明申请

WO1994015403A1 R/2R DIGITAL TO ANALOG CONVERTER 审中-公开
标题翻译： R / 2R数字到模拟转换器
公开(公告)号：WO1994015403A1
公开(公告)日：1994-07-07
申请号：PCT/EP1993003111
申请日：1993-11-05
申请人： VLSI TECHNOLOGY INC. , VALDENAIRE, Patrick
发明人： VLSI TECHNOLOGY INC.
IPC分类号： H03M01/78
CPC分类号： H03M1/785
摘要： A digital-to-analog converter of the R/2R ladder type is composed of two individually asymmetric ladders (51a, 51b) symmetrically coupled to a differential amplifier (16). Switch means (S1, etc.) in the shunt arms of the ladders are controlled so that the same number of shunt arms is connected to each of a pair of input or output nodes irrespective of the value of the controlling digital signal. The most significant shunt arm in each ladder may be configured as an equivalent (41, 42) of that part of the respective ladder extending from the respective stage node (10) towards the least significant end of the ladder.
摘要翻译： R / 2R梯形类型的数/模转换器由对称地耦合到差分放大器（16）的两个单独的不对称梯（51a，51b）组成。控制梯形分流臂中的开关装置（S1等），使得与一对输入或输出节点中的每一个连接相同数目的分流臂，而与控制数字信号的值无关。每个梯子中最重要的分流臂可以被配置为从相应的舞台节点（10）朝向梯子的最低有效端延伸的相应梯子的该部分的等同物（41,42）。

3. 发明专利

AU2003223080A1 MEMORY FOR TURBO DECODER 未知
公开(公告)号：AU2003223080A1
公开(公告)日：2003-12-02
申请号：AU2003223080
申请日：2003-05-07
申请人： VALDENAIRE PATRICK , KONINKL PHILIPS ELECTRONICS NV
发明人： CHARPENTIER SEBASTIEN
IPC分类号： H03M13/27 , H03M13/29 , H04L1/00
摘要： The decoding circuit comprises two decodes of type SISO (Soft-Input Soft-Output), a first decoder (14) and a second decoder (16), where each decoder can compute output extrinsic data on the basis of input extrinsic data issued by the other decoder, a memory store (31) for storing the extrinsic data, an interleaver (15) and a deinterleaver, that is an inverse interleaver (18). Output extrinsic data computed by a decoder are stored at an address of the output extrinsic data. The first decoder (14) reads the extrinsic data in a first order from the memory store (31), and the second decoder (16) reads the extrinsic data in a second order from the same memory store (31). The decoding is carried out by the decoding circuit (claimed) in an iterative manner, and the input data include a data vector (S1) and two parity vectors (P1,P2). The first order is a linear order, and the second orders is an interleaved order. The memory store comprises a read port and a write port. The memory store (31) is controlled by a clock of frequency two times higher than the frequency of the clock controlling the decoders (14,16), and also the decoder (20). In the third embodiment, the decoding circuit comprises a register for temporary storage of a component of a vector of input extrinsic data during the clock cycle controlling the decoders. The two decoders can be implemented by one decoder (20) also of type SISO, which functions alternatively according to a first mode corresponding to the functioning of the first decoder (14), and according to a second mode corresponding to the functioning of the second decoder (16). The decoding method (claimed) comprises a first step wherein the first decoder (14) reads in the linear manner the input extrinsic data stored in the memory (31), computes the output extrinsic data and writes each output extrinsic data at the address containing the corresponding input extrinsic data; and a second step wherein the second decoder (16) reads in the interleaved manner the input extrinsic data stored in the memory (31) and corresponding to the output extrinsic data computed by the first decoder (14) at the first step, computes the output extrinsic data and writes each output extrinsic data at the address containing the corresponding input extrinsic data. An electronic device (claimed) comprises the decoding circuit. A communication network (claimed) comprises at least one transmitter which can send coded signals, a transmission channel, a receiver which can receive the signals, and the decoding circuit. A program (claimed) comprises instructions of program code for executing the steps of the method when the program is executed on a processor.

4. 发明申请

WO03098811A8 MEMORY FOR TURBO DECODER 审中-公开
标题翻译：涡轮解码器的内存
公开(公告)号：WO03098811A8
公开(公告)日：2004-11-11
申请号：PCT/IB0301911
申请日：2003-05-07
申请人： KONINKL PHILIPS ELECTRONICS NV , CHARPENTIER SEBASTIEN , VALDENAIRE PATRICK
发明人： CHARPENTIER SEBASTIEN , VALDENAIRE PATRICK
IPC分类号： H03M13/27 , H03M13/29 , H04L1/00
CPC分类号： H03M13/2984 , H03M13/2782 , H03M13/2957 , H03M13/6563
摘要： The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.
摘要翻译：本发明涉及涡轮解码器的领域。这样的解码器包括第一解码器（14）和第二解码器（16），每个解码器能够从来自另一个解码器的外部输入数据计算外部输出数据。根据本发明的解码电路包括用于存储外在数据的单个存储器（31）。当解码器从来自另一个解码器的外部输入数据计算外部输出数据并存储在特定地址的单个存储器中时，该外部输出数据然后被写入该相同的地址。

5. 发明申请

WO03098811A2 MEMORY FOR TURBO DECODER 审中-公开
标题翻译：涡轮解码器的内存
公开(公告)号：WO03098811A2
公开(公告)日：2003-11-27
申请号：PCT/IB0301911
申请日：2003-05-07
申请人： KONINKL PHILIPS ELECTRONICS NV , CHARPENTIER SEBASTIEN , VALDENAIRE PATRICK
发明人： CHARPENTIER SEBASTIEN
IPC分类号： H03M13/27 , H03M13/29 , H04L1/00
CPC分类号： H03M13/2984 , H03M13/2782 , H03M13/2957 , H03M13/6563
摘要： The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.
摘要翻译：本发明涉及涡轮解码器的领域。这样的解码器包括第一解码器（14）和第二解码器（16），每个解码器能够从来自另一个解码器的外部输入数据计算外部输出数据。根据本发明的解码电路包括用于存储外在数据的单个存储器（31）。当解码器从来自另一个解码器的外部输入数据计算外部输出数据并存储在特定地址的单个存储器中时，该外部输出数据然后被写入该相同的地址。

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