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    • 2. 发明申请
    • MULTILEVEL VISUALIZATION OF SCENARIO MODELS AND SCENARIO INSTANCES
    • 场景模式和场景实验的多视觉化
    • US20130159037A1
    • 2013-06-20
    • US13326254
    • 2011-12-14
    • Ulrich KeilJoachim FesslerJochen MayerleUwe SchulzMarianne BroscheHolger Knospe
    • Ulrich KeilJoachim FesslerJochen MayerleUwe SchulzMarianne BroscheHolger Knospe
    • G06Q10/06
    • G06Q10/06
    • A single meta-model can include metadata defining a business scenario landscape that includes business scenarios accessible to members of an organization that are supported by a business software architecture. The metadata can include business process definitions and relationships between business processes. A user interface can present first, second, and/or third visualization layers based on the metadata. The first visualization layer can include first user interface elements forming a business scenario landscape map showing business scenarios and at least one relationship between the business scenarios. The second visualization layer can include second user interface elements displayed in a navigation pane concurrently with a work pane. The second user interface elements can represent a linear sequence of second business processes of a business scenario while the work pane can include additional user interface elements corresponding to functionality provided by the business software architecture relating to a currently selected business process.
    • 单个元模型可以包括定义业务场景景观的元数据,其中包括业务软件架构支持的组织成员可访问的业务场景。 元数据可以包括业务流程定义和业务流程之间的关系。 用户界面可以基于元数据呈现第一,第二和/或第三可视图层。 第一可视化层可以包括形成商业场景景观地图的第一用户界面元素,其显示业务场景和业务场景之间的至少一个关系。 第二可视化层可以包括与工作窗格同时显示在导航窗格中的第二用户界面元素。 第二用户界面元素可以表示业务场景的第二业务流程的线性序列,而工作窗格可以包括对应于与当前选择的业务过程相关的业务软件体系结构提供的功能的附加用户界面元素。
    • 7. 发明授权
    • Method for physical VLSI-chip design
    • 物理VLSI芯片设计方法
    • US4890238A
    • 1989-12-26
    • US133402
    • 1987-12-15
    • Klaus KleinKurt PollmannHelmut SchettlerUwe SchulzOtto M. WagnerRainer Zuehlke
    • Klaus KleinKurt PollmannHelmut SchettlerUwe SchulzOtto M. WagnerRainer Zuehlke
    • H01L21/82G06F17/50H01L21/822H01L27/04
    • G06F17/5072
    • For the physical design of a very large scale integration (VSLI) chip, a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology, the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus, the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.
    • 对于大规模集成(VSLI)芯片的物理设计,提供了一种实现包含逻辑和RAM的高密度主映像的方法。 在分层自顶向下的设计方法中,芯片上所包含的电路在逻辑上划分为可由当前自动设计系统和程序管理的分区。 全局接线连接线从一开始就包括在不同的分区设计中,并以与该区域的电路相同的方式进行处理。 因此,不同的分区是并行设计的。 建立了平面图,其给出不同分区的形状,使得它们在不在不同单独分区之间留下空间的情况下相配合。 该芯片不需要额外的空间用于全局布线,并且分区立即相互连接。 所描述的主图像对逻辑,RAM,ROM和其他宏非常灵活,并且提供半定制门阵列和定制宏设计的一些优点。 这样设计的芯片在分区之间没有显示全局布线通道,并具有不同孔隙度的分隔。