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1. 发明授权

US5606676A Branch prediction and resolution apparatus for a superscalar computer processor 失效
标题翻译：用于超标量计算机处理器的分支预测和分辨率装置
公开(公告)号：US5606676A
公开(公告)日：1997-02-25
申请号：US386066
申请日：1995-02-09
申请人： Edward T. Grochowski , Donald B. Alpert , Jack D. Mills , Uri C. Weiser
发明人： Edward T. Grochowski , Donald B. Alpert , Jack D. Mills , Uri C. Weiser
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/30192 , G06F9/3806 , G06F9/3812 , G06F9/3836 , G06F9/3844 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction.
摘要翻译：一种使用预测分支正确的分支预测和验证来提高超标量流水线计算机性能的装置和方法。预测分支可以在两个不同流水线阶段之一中解决，并且提供了一种用于处理在任一流水线阶段中解决的分支的方法。提供一种分支验证方法，其验证架构上正确的指令处于解码和执行阶段。此外，当多时钟指令需要多个时钟解码时，提供两组预取缓冲器以允许分支预测。

2. 发明授权

US5442756A Branch prediction and resolution apparatus for a superscalar computer processor 失效
标题翻译：用于超标量计算机处理器的分支预测和分辨率装置
公开(公告)号：US5442756A
公开(公告)日：1995-08-15
申请号：US922855
申请日：1992-07-31
申请人： Edward T. Grochowski , Donald B. Alpert , Jack D. Mills , Uri C. Weiser
发明人： Edward T. Grochowski , Donald B. Alpert , Jack D. Mills , Uri C. Weiser
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/30192 , G06F9/3806 , G06F9/3812 , G06F9/3836 , G06F9/3844 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction.
摘要翻译：一种使用预测分支正确的分支预测和验证来提高超标量流水线计算机性能的装置和方法。预测分支可以在两个不同流水线阶段之一中解决，并且提供了一种用于处理在任一流水线阶段中解决的分支的方法。提供一种分支验证方法，其验证架构上正确的指令处于解码和执行阶段。此外，当多时钟指令需要多个时钟解码时，提供两组预取缓冲器以允许分支预测。

3. 发明申请

US20090285207A1 SYSTEM AND METHOD FOR ROUTING PACKETS USING TAGS 审中-公开
标题翻译：使用标签路由包的系统和方法
公开(公告)号：US20090285207A1
公开(公告)日：2009-11-19
申请号：US12120656
申请日：2008-05-15
申请人： Yochai COHEN , Michael Chaim Schnarch , Uri C. Weiser
发明人： Yochai COHEN , Michael Chaim Schnarch , Uri C. Weiser
IPC分类号： H04L12/56
CPC分类号： H04L63/0236
摘要： A system and method for controlling traffic in a packet-based communication system is disclosed. A number indicative of the source of a request packet may be modified to receive a shifted source number which may be, according to embodiments of the invention, in an unused shifted range of source numbers. A destination number in a received packet may be extracted and if it is in the shifted range of port numbers that packet may be determined as a response packet, the shifted port number may be un-shifted back and its restored value may be used to direct that packet to the device which issued the request, substantially without having to extract any additional information from the packet.
摘要翻译：公开了一种用于控制基于分组的通信系统中的业务的系统和方法。可以修改指示请求分组的源的数字，以接收根据本发明的实施例的移动的源号码，其处于未使用的源号码的移位范围内。可以提取接收到的分组中的目的地号码，并且如果它在端口号的移位范围内，分组可以被确定为响应分组，则可以将移位的端口号未被移回，并且其恢复的值可以用于引导该分组发送到发送请求的设备，基本上不必从分组中提取任何附加信息。

4. 发明授权

US09003421B2 Acceleration threads on idle OS-visible thread execution units 有权
标题翻译：空闲OS可见线程执行单元上的加速线程
公开(公告)号：US09003421B2
公开(公告)日：2015-04-07
申请号：US11288823
申请日：2005-11-28
申请人： Ron Gabor , Gad Sheaffer , Avi Mendelson , Uri C. Weiser , Hong Wang
发明人： Ron Gabor , Gad Sheaffer , Avi Mendelson , Uri C. Weiser , Hong Wang
IPC分类号： G06F9/46 , G06F9/30 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4843 , G06F9/461 , G06F9/5027 , G06F2209/5018
摘要： Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non-idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.
摘要翻译：公开了使用空闲螺纹单元执行对操作系统透明的加速度线程的系统，方法和机构的实施例。当操作系统调度器没有在空闲线程单元上进行调度时，操作系统可以发出停止或监视/等待或其他指令来将线程单元置于空闲状态。当线程单元处于空闲状态时，从操作系统的角度来看，线程单元可用于执行推测加速线程，以加速在非空闲线程单元上运行的线程。空闲线程单元的上下文在执行加速线程之前被保存，并且当操作系统需要使用线程单元时被恢复。加速线程对操作系统是透明的。还描述和要求保护其他实施例。

5. 发明授权

US5265213A Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction 失效
标题翻译：用于与执行分支指令同时执行预测分支目标指令的管线系统
公开(公告)号：US5265213A
公开(公告)日：1993-11-23
申请号：US625761
申请日：1990-12-10
申请人： Uri C. Weiser , David Perlmutter , Yaakov Yaari
发明人： Uri C. Weiser , David Perlmutter , Yaakov Yaari
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3844
摘要： A pipeline instruction processor for executing instructions stored in an instruction memory, including a plurality of branch instructions. The instruction processor includes a branch target buffer which contains target instructions and target addresses corresponding to branch instructions. The target instruction data is indexed according to the address of the instruction which precedes the branch instruction. Also included in the branch target buffer is history data indicating whether the branch was taken. The instruction processor also includes two execution units. The present invention employs logic which allows a branch instruction and its target instruction stored in the branch target buffer to be executed concurrently in the two execution units according to the history data stored in the branch target buffer. Since the branch instructions and their target instructions are executed during the same cycle, branch instructions appear to be executed in zero cycles.
摘要翻译：一种用于执行存储在指令存储器中的指令的流水线指令处理器，包括多个分支指令。指令处理器包括分支目标缓冲器，其包含与分支指令对应的目标指令和目标地址。目标指令数据根据分支指令之前的指令的地址进行索引。还包括在分支目标缓冲器中的是指示分支是否被采取的历史数据。指令处理器还包括两个执行单元。本发明采用根据存储在分支目标缓冲器中的历史数据，允许在两个执行单元中同时执行存储在分支目标缓冲器中的分支指令及其目标指令的逻辑。由于分支指令及其目标指令在同一周期内执行，所以分支指令似乎以零周期执行。

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