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1. 发明授权

US07196369B2 Plasma damage protection circuit for a semiconductor device 有权
标题翻译：半导体器件的等离子体损伤保护电路
公开(公告)号：US07196369B2
公开(公告)日：2007-03-27
申请号：US10195706
申请日：2002-07-15
申请人： Ming Hung Chou , Tu Shun Chen , Smile Huang
发明人： Ming Hung Chou , Tu Shun Chen , Smile Huang
IPC分类号： H01L29/788
CPC分类号： H01L27/092 , H01L27/1052 , H01L27/11521 , H01L27/11568
摘要： A protection device and a method for manufacturing integrated circuit devices protect against plasma charge damage, and related charge damage during manufacture. The protection device comprises a dynamic threshold, NMOS/PMOS pair having their respective gate terminals coupled to the semiconductor bulk in which the channel regions are formed. With proper metal connection, the structure protects against plasma charge damage on the integrated circuit device during manufacture, and can also be operated to protect against abnormal voltages during operation of the circuit.
摘要翻译：集成电路器件的保护装置和制造方法可防止等离子体电荷损坏，以及制造期间相关的电荷损坏。保护装置包括动态阈值，NMOS / PMOS对具有耦合到半导体体的各自的栅极端子，其中形成沟道区域。通过适当的金属连接，该结构可防止在制造过程中对集成电路器件造成的等离子体电荷损坏，并且还可以在电路运行期间进行操作以防止异常电压。

2. 发明授权

US06396753B1 Method and structure for testing embedded flash memory 有权
标题翻译：嵌入式闪存测试方法和结构
公开(公告)号：US06396753B1
公开(公告)日：2002-05-28
申请号：US09826497
申请日：2001-04-05
申请人： Chun-Hsiung Hung , Nai-Ping Kuo , Tu-Shun Chen , Ho-Chun Liou
发明人： Chun-Hsiung Hung , Nai-Ping Kuo , Tu-Shun Chen , Ho-Chun Liou
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C16/04 , G11C2207/104
摘要： A method and structure for testing embedded flash memory including a memory array and a logic element. A control transistor is disposed and is connected between a sense amplifier and an I/O buffer in the memory array, and a speed control pin connected to the logic element in one terminal is coupled to the gate terminal of the control transistor in the other terminal to switch the control transistor on or off. Turning off the control transistor after a test time by the speed control pin closes the channel between the sense amplifier and I/O buffer, and an output signal from the memory array to a test system connected to the logic element is detected with the test system to determine an access time of the memory array.
摘要翻译：一种用于测试包括存储器阵列和逻辑元件的嵌入式闪速存储器的方法和结构。控制晶体管被设置并连接在存储器阵列中的读出放大器和I / O缓冲器之间，并且连接到一个端子中的逻辑元件的速度控制引脚耦合到另一个端子中的控制晶体管的栅极端子开关控制晶体管。通过速度控制引脚在测试时间后关闭控制晶体管，关闭读出放大器和I / O缓冲器之间的通道，并从测试系统检测到从存储器阵列到连接到逻辑元件的测试系统的输出信号以确定存储器阵列的访问时间。

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