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1. 发明授权

US4466127A Entry apparatus of digital value in memory 失效
标题翻译：存储器中数字值输入装置
公开(公告)号：US4466127A
公开(公告)日：1984-08-14
申请号：US39454
申请日：1979-05-16
申请人： Tsutomu Ohgishi , Tadashi Sakurai
发明人： Tsutomu Ohgishi , Tadashi Sakurai
IPC分类号： H03L7/18 , H03J5/00 , H03J5/02 , H03J7/28 , H03L7/183 , H03M1/00
CPC分类号： H03J5/0281 , H03J5/0263 , H03M1/56
摘要： A radio receiver having a counter which generates a count value corresponding to the frequency of a station to be received which value is stored in a memory through a load enable signal produced when a ramp voltage reaches a value corresponding to a comparison voltage set to correspond to the frequency. The stored count value controls a programmable divider of a phase lock loop circuit to cause the oscillator of the circuit to produce the correct local oscillator frequency to be received. An N-nary counter permits only every Nth count value to be stored in the memory to correspond to the frequency spacing between stations.
摘要翻译：一种无线电接收机，具有计数器，该计数器通过当斜坡电压达到对应于对应于比较电压的比较电压的值时产生的负载使能信号，产生对应于待接收站的频率的计数值，该值存储在存储器中频率。存储的计数值控制锁相环电路的可编程分频器，使得电路的振荡器产生要接收的正确的本地振荡器频率。 N-Nary计数器仅允许每N个计数值存储在存储器中以对应于站之间的频率间隔。

2. 发明授权

US4216451A Variable capacitance device having a plurality of capacitance elements and a plurality of switching elements therefor formed on a single common substrate 失效
标题翻译：可变电容器件具有形成在单个公共衬底上的多个电容元件和多个开关元件
公开(公告)号：US4216451A
公开(公告)日：1980-08-05
申请号：US885281
申请日：1978-03-10
申请人： Itsuro Nishimura , Tsutomu Ohgishi
发明人： Itsuro Nishimura , Tsutomu Ohgishi
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/06 , H03J3/18 , H03J5/02 , H03J5/24
CPC分类号： H03J3/185 , H03J5/244 , H03J2200/10
摘要： A variable capacitance semiconductor device is provided wherein a plurality of capacitance elements each having a fixed capacitance value are coupled in parallel with each other and at least two insulated gate field effect transistors are provided for each of the plurality of capacitance elements, whereby the total length of the insulated gate field effect transistors is made as long as possible and accordingly the resistance across the transistors when these are turned on becomes small. Each capacitance element may comprise a single semiconductor substrate of one conductivity type, an opposite conductivity type region formed on one surface of the substrate, an insulating layer formed on the opposite conductivity type region and an electrode formed on the insulating layer. The above described at least two insulated gate field effect transistors are formed such that the above described substrate is shared. Preferably, a direct current voltage is applied to the opposite conductivity type region in the direction for decreasing the junction capacitance between the opposite conductivity type region and the substrate occuring when the above described transistors are turned off.
摘要翻译：提供了一种可变电容半导体器件，其中具有固定电容值的多个电容元件彼此并联耦合，并且为多个电容元件中的每一个设置至少两个绝缘栅场效应晶体管，由此，绝缘栅场效应晶体管的长度尽可能长，因此当晶体管导通时，两端的电阻变小。每个电容元件可以包括一个导电类型的单个半导体衬底，形成在衬底的一个表面上的相反导电类型区域，形成在相反导电类型区域上的绝缘层和形成在绝缘层上的电极。上述至少两个绝缘栅场效应晶体管形成为使得上述基板共享。优选地，当上述晶体管截止时，在相反导电类型区域和衬底之间的结电容的方向上，向相反导电类型区域施加直流电压。

3. 发明授权

US4352204A Entry apparatus of digital value in memory 失效
标题翻译：存储器中数字值输入装置
公开(公告)号：US4352204A
公开(公告)日：1982-09-28
申请号：US79537
申请日：1979-09-27
申请人： Tsutomu Ohgishi , Tadashi Sakurai
发明人： Tsutomu Ohgishi , Tadashi Sakurai
IPC分类号： H03J5/02 , H03M1/00 , H03J5/00
CPC分类号： H03J5/0281 , H03J5/0263 , H03M1/56
摘要： The reference signal output from a reference oscillator is applied to a counter where the reference signal is counted to provide a count output as a changeable digital value. A saw-tooth wave generator is provided so as to generate a saw-tooth wave such that the saw-tooth wave is changeable of the waveform in synchronism with the count output. A comparison voltage generator is also provided which may typically comprise a variable resistor. A load enable signal generator is provided to receive the saw-tooth wave output from the saw-tooth wave generator and the comparison voltage output as set in the comparison voltage generator. The load enable signal generator is structured to compare the saw-tooth wave output and the comparison voltage output to provide a load enable signal whenever both outputs coincide with each other. A digital memory is provided to be responsive to the load enable signal from the load enable signal generator to load therein the count output representing a digital value in the counter which has been attained when the load enable signal is obtained.
摘要翻译：从参考振荡器输出的参考信号被施加到计数器，其中参考信号被计数以提供计数输出作为可变数字值。锯齿波发生器被设置成产生锯齿波，使得锯齿波可以与计数输出同步地改变波形。还提供了比较电压发生器，其可以典型地包括可变电阻器。提供负载使能信号发生器以接收从锯齿波发生器输出的锯齿波和比较电压产生器中设置的比较电压输出。负载使能信号发生器被构造为比较锯齿波输出和比较电压输出，以便每当两个输出彼此重合时提供负载使能信号。提供数字存储器以响应于来自负载使能信号发生器的负载使能信号来加载其中表示在获得负载使能信号时已达到的计数器中的数字值的计数输出。

4. 发明授权

US4236251A Frequency synthesizer receiver having memory for storing frequency data 失效
标题翻译：具有用于存储频率数据的存储器的频率合成器接收器
公开(公告)号：US4236251A
公开(公告)日：1980-11-25
申请号：US837761
申请日：1977-09-29
申请人： Tsutomu Ohgishi , Toru Akiyama , Tadashi Sakurai
发明人： Tsutomu Ohgishi , Toru Akiyama , Tadashi Sakurai
IPC分类号： H03J7/18 , H03J5/02 , H03J7/28 , H04B1/26
CPC分类号： H03J5/0281
摘要： A digital frequency synthesizer radio receiver, comprising a scan memory for storing a digital value data concerning a broadcasting frequency; a digital value data entry device for selectively entering a digital value concerning a broadcasting frequency; a preset memory having a plurality of storing locations, each adapted for storing a digital value concerning a specified broadcasting frequency, a channel selector coupled to said preset memory for selecting one of said storing locations thereof, said preset memory being responsive to said channel selector and said digital value data entry device for loading the entered digital value data in the location of the preset memory selected by the channel selector; and a phase locked loop selectively and operatively coupled to either of said scan memory and said preset memory for providing an oscillation frequency signal the frequency of which is associated with the digital value data loaded in the selected one of said scan memory and the preset memory. Preferably, said scan memory comprises a plurality of memories, each allotted for a frequency band, and said preset memory is structured such that each location comprises a plurality of regions, each allotted for a frequency band, whereby a multiband frequency synthesizer radio receiver is provided.
摘要翻译：一种数字频率合成器无线电接收机，包括用于存储关于广播频率的数字值数据的扫描存储器; 数字值数据输入装置，用于选择性地输入关于广播频率的数字值; 具有多个存储位置的预设存储器，每个存储位置适于存储关于指定广播频率的数字值;频道选择器，耦合到所述预设存储器，用于选择所述存储位置之一，所述预设存储器响应于所述频道选择器和所述数字值数据输入装置用于将输入的数字值数据加载到由频道选择器选择的预设存储器的位置中; 以及锁相环，其选择性地和操作地耦合到所述扫描存储器和所述预设存储器中的任一个，以提供其频率与加载在所述扫描存储器和所述预置存储器中所选择的一个中的数字值数据相关联的振荡频率信号。优选地，所述扫描存储器包括多个存储器，每个存储器被分配用于频带，并且所述预设存储器被构造为使得每个位置包括多个区域，每个区域被分配用于频带，由此提供多频带合成器无线电接收机。

5. 发明授权

US4179628A Flip-flop having reset preferential function 失效
标题翻译：触发器具有复位优先功能
公开(公告)号：US4179628A
公开(公告)日：1979-12-18
申请号：US853584
申请日：1977-11-21
申请人： Tsutomu Ohgishi , Toru Akiyama , Tadashi Sakurai
发明人： Tsutomu Ohgishi , Toru Akiyama , Tadashi Sakurai
IPC分类号： H03K3/037 , H03K3/356 , H03K3/286 , H03D13/00 , H03K3/353 , H03K5/20
CPC分类号： H03K3/037 , H03K3/356017 , H03K3/356052
摘要： A flip-flop having a reset preferential function, comprising a set input terminal, a reset input terminal, a clock signal source operatively coupled through a field effect transistor to the set input terminal, a capacitance formed at the gate electrode of the field effect transistor, a charge control transistor controllable responsive to the clock signal for precharging the capacitance prior to the clock signal, a discharge control transistor controllable responsive to the reset signal for discharging the capacitance, whereby the capacitance is precharged prior to the clock signal and is discharged responsive to the reset signal, the field effect transistor being rendered conductive as a function of the electric charge of the capacitance, the clock signal source being operatively coupled to the set input terminal as a function of the conduction state of the field effect transistor, whereby the flip-flop is set responsive to the leading edge of the clock signal and is reset responsive to the reset signal in preference to the clock signal.
摘要翻译：具有复位优先功能的触发器，包括设置输入端子，复位输入端子，通过场效应晶体管可操作地耦合到设定输入端子的时钟信号源，形成在场效应晶体管的栅电极处的电容，电荷控制晶体管，其可响应于时钟信号控制，用于在时钟信号之前对电容进行预充电，放电控制晶体管可响应于用于放电电容的复位信号而受控制，由此在时钟信号之前预先充电电容并且响应于放电对于复位信号，场效应晶体管作为电容的电荷的函数而导通，时钟信号源作为场效应晶体管的导通状态的函数被可操作地耦合到设置的输入端，由此，触发器设置为响应于时钟信号的前沿，并且响应于t而被复位 o优先于时钟信号的复位信号。

6. 发明授权

US4201945A Phase comparing apparatus 失效
标题翻译：相位比较装置
公开(公告)号：US4201945A
公开(公告)日：1980-05-06
申请号：US903789
申请日：1978-05-08
申请人： Tsutomu Ohgishi , Toru Akiyama , Tadashi Sakurai
发明人： Tsutomu Ohgishi , Toru Akiyama , Tadashi Sakurai
IPC分类号： G01R25/00 , H03L7/095 , H04B1/06
CPC分类号： G01R25/00 , H03L7/095 , Y10S331/02
摘要： A lock detecting circuit of a phase locked loop, comprising a phase comparator for receiving a reference frequency signal and a signal being compared with the reference frequency signal, a charging/discharging circuit which is charge/discharge controlled responsive to the output of the phase comparator and either of the above described two signals, and a delay flip-flop responsive to the output of the charging/discharging circuit and in synchronism with the signal applied to the charging/discharging circuit for assuming one storing state for providing an output representative of the phase difference between the above described two signals.
摘要翻译：锁相环的锁定检测电路，包括用于接收参考频率信号的相位比较器和与参考频率信号进行比较的信号;响应于相位比较器输出的充/放电控制的充电/放电电路和上述两个信号中的任一个，以及响应于充电/放电电路的输出的延迟触发器，并且与施加到充电/放电电路的信号同步，以假设一个存储状态，以提供代表上述两个信号之间的相位差。

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