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    • 9. 发明授权
    • Continuous data server apparatus and method for controlling continuous
data server
    • 连续数据服务器设备及控制连续数据服务器的方法
    • US5875475A
    • 1999-02-23
    • US707940
    • 1996-09-10
    • Toshiki KizuTatsunori KanaiHiroshi YaoSeiji Maeda
    • Toshiki KizuTatsunori KanaiHiroshi YaoSeiji Maeda
    • G06F13/00G06F3/06H04N5/76H04N7/173
    • H04N7/17336
    • A continuous data server capable of reducing a cost for issuing control commands from a central control device to data memory control devices and communication control devices. The central control device issues a control command for each data memory control device and a control command for each communication control device collectively as a single control command set. Alternatively, the central control device issues control commands for the data memory control devices collectively as a single first control command set, and control commands for the communication control devices collectively as a single second control command set, through separately provided communication paths. When the continuous data are striped over data memory devices, the central control device can issue a common control command for all the data memory control devices.
    • 一种连续的数据服务器,其能够降低从中央控制装置向数据存储器控制装置和通信控制装置发出控制命令的成本。 中央控制装置将每个数据存储器控制装置的控制命令和每个通信控制装置的控制命令一起作为单个控制命令集发出。 或者,中央控制装置通过单独提供的通信路径,将数据存储器控制装置的控制命令统一地发送为单个第一控制命令集,以及将通信控制装置的控制命令集体地统一为单个第二控制命令集。 当连续数据在数据存储设备上分条时,中央控制设备可以为所有的数据存储器控制设备发出一个共同的控制命令。
    • 10. 发明授权
    • Multi-core processor system with thread queue based power management
    • 具有线程队列功能管理的多核处理器系统
    • US08214679B2
    • 2012-07-03
    • US12610472
    • 2009-11-02
    • Yuji IshikawaToshiki KizuRyuichiro Ohyama
    • Yuji IshikawaToshiki KizuRyuichiro Ohyama
    • G06F1/32
    • G06F9/4893G06F1/3228G06F9/5027G06F9/5094G06F2209/5018Y02D10/22Y02D10/24
    • A multi-core processor system includes: a plurality of processor cores; a power supply unit that stops supplying or supplies power to each of the processor cores individually; and a thread queue that stores threads that the multi-core processor system causes the processor cores to execute. Each of the processor cores includes: a power-supply stopping unit that causes the power supply unit to stop power supply to an own processor core when a number of threads stored in the thread queue is equal to or smaller than a first threshold; and a power-supply resuming unit that causes the power supply unit to resume power supply to the other stopped processor cores when the number of threads stored in the thread queue exceeds a second value equal to or lager than the first threshold.
    • 多核处理器系统包括:多个处理器核; 电源单元,其分别停止向每个处理器核心供电或供电; 以及存储多核处理器系统使处理器核心执行的线程的线程队列。 每个处理器核心包括:电源停止单元,当存储在线程队列中的线程数等于或小于第一阈值时,使电源单元停止向自己的处理器核心供电; 以及电源恢复单元,当存储在所述线程队列中的线程数超过等于或大于所述第一阈值的第二值时,所述电源恢复单元使得所述电源单元恢复向所述其他停止的处理器核心的电力供应。