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    • 1. 发明专利
    • Operational amplifier
    • 操作放大器
    • JP2010041645A
    • 2010-02-18
    • JP2008205445
    • 2008-08-08
    • Toshiba CorpToshiba Discrete Technology Kk東芝ディスクリートテクノロジー株式会社株式会社東芝
    • TODA SHUJIHASEGAWA MASAHIRO
    • H03F3/45
    • PROBLEM TO BE SOLVED: To provide an operational amplifier in which the flatness of mutual conductance is improved in a wide common-mode input voltage range.
      SOLUTION: The operational amplifier includes: a differential input circuit provided with first and second differential pairs and supplied with a first power supply voltage and a second power supply voltage lower than the first power supply voltage; and a control circuit capable of detecting that an FET configuring the first differential pair is operated in the case that a common-mode input voltage between the first power supply voltage and the second power supply voltage is inputted to the first and second differential pairs respectively, and adjusting the operation of an FET configuring the second differential pair so as to keep the mutual conductance of the differential input circuit at a roughly fixed value.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供一种在广泛的共模输入电压范围内提高互导的平坦度的运算放大器。 解决方案:运算放大器包括:差分输入电路,设有第一和第二差分对,并提供第一电源电压和低于第一电源电压的第二电源电压; 以及控制电路,其能够检测在所述第一电源电压和所述第二电源电压之间的共模输入电压分别输入到所述第一和第二差分对的情况下,构成所述第一差分对的FET, 以及调整构成所述第二差分对的FET的操作,以使差分输入电路的互导体保持大致固定的值。 版权所有(C)2010,JPO&INPIT
    • 3. 发明专利
    • Negative feedback amplifier
    • 负反馈放大器
    • JP2010004258A
    • 2010-01-07
    • JP2008160528
    • 2008-06-19
    • Toshiba CorpToshiba Discrete Technology Kk東芝ディスクリートテクノロジー株式会社株式会社東芝
    • TODAKA JUNICHITODA SHUJI
    • H03F1/32G05F1/56
    • PROBLEM TO BE SOLVED: To compensate a phase even if an output voltage is reduced to a reference voltage in a negative feedback amplifier.
      SOLUTION: A voltage regulator 50 is a tri-level negative feedback amplifier, and has a phase compensation circuit 5 having D-type Nch MOS transistors DNT1 and DNT2. A drain of the D-type Nch MOS transistor DNT1 is connected to a drain of an E-type Nch MOS transistor NT1 of a first stage amplifying circuit 1, and a gate is connected to a low potential side power (ground electric potential) VSS. The D-type Nch MOS transistor DNT2, which forms a differential pair with the D-type Nch MOS transistor DNT1, is connected to a drain of an E-type Nch MOS transistor NT2 of the first stage amplifying circuit 1, and a feedback voltage Ve1 outputted from a high-pass filter composed of a capacitor C2 and a resistor R4 is inputted to the gate. A feedback voltage Ve2 subjected to resistance division is inputted to the gate of the E-type Nch MOS transistor NT2.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:即使在负反馈放大器中输出电压降低到参考电压,也可以补偿相位。 解决方案:电压调节器50是三电平负反馈放大器,并且具有具有D型N沟道MOS晶体管DNT1和DNT2的相位补偿电路5。 D型N沟MOS晶体管DNT1的漏极连接到第一级放大电路1的E型Nch MOS晶体管NT1的漏极,栅极连接到低电位侧电源(接地电位)VSS 。 与D型Nch MOS晶体管DNT1形成差分对的D型Nch MOS晶体管DNT2连接到第一级放大电路1的E型Nch MOS晶体管NT2的漏极,反馈电压 从由电容器C2和电阻器R4组成的高通滤波器输出的Ve1被输入到门。 经过电阻分割的反馈电压Ve2被输入到E型Nch MOS晶体管NT2的栅极。 版权所有(C)2010,JPO&INPIT
    • 4. 发明专利
    • Optical coupling device circuit and optical coupling device
    • 光耦合器件电路和光耦合器件
    • JP2009302210A
    • 2009-12-24
    • JP2008153479
    • 2008-06-11
    • Toshiba CorpToshiba Discrete Technology Kk東芝ディスクリートテクノロジー株式会社株式会社東芝
    • FUJITA MASAMI
    • H01L31/12
    • PROBLEM TO BE SOLVED: To provide an optical coupling device circuit and an optical coupling device in which light-emitting elements have improved responsiveness. SOLUTION: The optical coupling device circuit includes a light-emitting element 17 whose light emission is controlled with a drive signal inputted through a capacitor 12 and a resistance 13 connected in parallel to each other forming a speed-up circuit 14, a light-emitting element 37 controlled with a signal which is input through a capacitor 32 and a resistance 33 connected in parallel to each other forming a speed-up circuit 34 and is opposite in phase to the drive signal, and phototransistors 21 and 41 which are insulated from the light-emitting elements 17 and 37, respectively, and respond to light emission signals of the light-emitting elements 17 and 37 and are connected in series with each other. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供一种光耦合器件电路和光耦合器件,其中发光元件具有改善的响应性。 解决方案:光耦合器件电路包括发光部,其发光通过电容器12输入的驱动信号和彼此并联连接形成加速电路14的电阻13进行控制, 发光元件37由通过电容器32输入的信号和彼此并联连接的电阻33控制,形成加速电路34并且与驱动信号相位相反,光电晶体管21和41是 与发光元件17和37分别绝缘,并响应于发光元件17和37的发光信号并且彼此串联连接。 版权所有(C)2010,JPO&INPIT
    • 5. 发明专利
    • Semiconductor light-emitting element and method for manufacturing the same, and epitaxial wafer
    • 半导体发光元件及其制造方法和外延波形
    • JP2009260136A
    • 2009-11-05
    • JP2008109205
    • 2008-04-18
    • Toshiba CorpToshiba Discrete Technology Kk東芝ディスクリートテクノロジー株式会社株式会社東芝
    • DEI YASUO
    • B82Y10/00B82Y20/00B82Y40/00H01L21/205H01L33/30
    • PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element capable of performing high-luminescence and long-term stable operation while crystallinity is improved, and to provide a method for manufacturing the element, and an epitaxial wafer. SOLUTION: The semiconductor light-emitting element includes a GaP substrate in a range of 3×10 17 to 1×10 18 cm -3 in a carrier concentration, a bonding layer with a first surface side bonded to the GaP substrate, and an upper growing layer formed on a second surface side facing the first surface side of the bonding layer and provided with a light emitting layer capable of emitting light which can be transmitted through the GaP substrate while the deviation of a lattice from the bonding layer is smaller than that between the GaP substrate and the bonding layer. Such a semiconductor light-emitting element, its manufacturing method, and the epitaxial wafer are provided. COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题:提供一种能够在结晶度提高的同时进行高发光和长期稳定操作的半导体发光元件,并提供一种用于制造元件的方法和外延晶片。 解决方案:半导体发光元件包括在3×10 17 至1×10 18 cm -3的范围内的GaP衬底。 SP>载流子浓度,具有与GaP基板接合的第一表面侧的接合层和形成在面向接合层的第一表面侧的第二表面侧上的上部生长层,并且设置有能够 发射可以透过GaP衬底的光,同时晶格与结合层的偏离比GaP衬底和结合层之间的偏差小。 提供这样的半导体发光元件,其制造方法和外延晶片。 版权所有(C)2010,JPO&INPIT
    • 6. 发明专利
    • Dc-dc converter
    • DC-DC转换器
    • JP2008228461A
    • 2008-09-25
    • JP2007063946
    • 2007-03-13
    • Toshiba CorpToshiba Discrete Technology Kk東芝ディスクリートテクノロジー株式会社株式会社東芝
    • KASAI KEIOZAKI KAORU
    • H02M3/155
    • PROBLEM TO BE SOLVED: To suppress the drop of output voltage and to prevent the deterioration of a load response characteristic even if input voltage rapidly drops and load fluctuation occurs.
      SOLUTION: A DC-DC converter includes an inductor element L1, synchronous rectification switching elements Q1 and Q2, an error amplifier 1, a phase compensation circuit 2, a current detecting circuit 3, a slope compensation circuit 4, a PWM comparator 5, an oscillation circuit 6, a first RS latch circuit 7, a second RS latch circuit 8, a control logic circuit 9, driver circuits 10 and 11, a clock generating circuit 12, a duty detecting circuit 13 and resistors R1 and R2. Even if a duty ratio exceeds 100%, a processing for shortening the duty ratio is not performed and an oscillation operation of the oscillation circuit 6 is compulsorily stopped. Even if input voltage VIN largely fluctuates, fluctuation of output voltage VOUT can be suppressed and an input/output voltage VOUT difference can be reduced.
      COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:即使输入电压急剧下降并且负载波动发生,也可以抑制输出电压的下降,防止负载响应特性的劣化。 解决方案:DC-DC转换器包括电感器元件L1,同步整流开关元件Q1和Q2,误差放大器1,相位补偿电路2,电流检测电路3,斜率补偿电路4,PWM比较器 5,振荡电路6,第一RS锁存电路7,第二RS锁存电路8,控制逻辑电路9,驱动电路10和11,时钟发生电路12,占空比检测电路13和电阻R1和R2。 即使占空比超过100%,也不进行缩短占空比的处理,强制停止振荡电路6的振荡动作。 即使输入电压VIN大幅波动,也能够抑制输出电压VOUT的波动,能够降低输入输出电压VOUT的差。 版权所有(C)2008,JPO&INPIT
    • 10. 发明专利
    • Envelope for optical semiconductor element and optical semiconductor device using the same
    • 光学半导体元件和使用该光学半导体器件的光学半导体器件的封装
    • JP2007005722A
    • 2007-01-11
    • JP2005187045
    • 2005-06-27
    • Toshiba CorpToshiba Discrete Technology Kk東芝ディスクリートテクノロジー株式会社株式会社東芝
    • ONO REIJI
    • H01L33/52H01L33/58
    • H01L2224/48091H01L2224/48227H01L2224/48465H01L2924/00014H01L2924/00
    • PROBLEM TO BE SOLVED: To provide an envelope for an optical semiconductor element which can prevent the leakage of resin filled in a recess and obtain a plate light ejecting surface, and an optical semiconductor device using the envelope.
      SOLUTION: The envelope 10 is provided with a base board 11 forming a recess 16 on the upper surface, and forming a projected part 17 projected to the inside of a periphery on the opened end of the recess 16; first and second electrode leads 18, 19 formed on the base board 11 and exposed to the bottom of the recess 16; and first and second external terminals 20, 21 respectively electrically connected to the first and second electric leads 18, 19, and formed on the outer wall surface of the base board 11. The optical semiconductor device is provided with the envelope 10, an optical semiconductor element 31 mounted on the first electrode lead 18 in the recess 16, a connection conductor 32 for electrically connecting the optical semiconductor element 31 to the second electrode lead 19, and sealing resin 33 filled in the recess 16 up to a projected part 17.
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供一种可以防止填充在凹部中的树脂的泄漏并获得板光弹出表面的光学半导体元件的包络体,以及使用该外壳的光学半导体器件。 解决方案:外壳10设置有在上表面上形成凹部16的基板11,并且形成在凹部16的开口端上突出到周边内侧的突出部17; 形成在基板11上并暴露于凹部16的底部的第一和第二电极引线18,19; 以及分别电连接到第一和第二电引线18,19并形成在基板11的外壁表面上的第一和第二外部端子20,21。光学半导体器件设置有外壳10,光学半导体 安装在凹部16中的第一电极引线18上的元件31,用于将光学半导体元件31电连接到第二电极引线19的连接导体32,以及填充在凹部16中的密封树脂33直到突出部17。 P>版权所有(C)2007,JPO&INPIT