专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08211494B2 Method and apparatus for manufacturing circuit board 失效
标题翻译：制造电路板的方法和装置
公开(公告)号：US08211494B2
公开(公告)日：2012-07-03
申请号：US10540606
申请日：2004-12-15
申请人： Toshiaki Takenaka , Toshikazu Kondou , Yukihiro Hiraishi , Kunio Kishimoto
发明人： Toshiaki Takenaka , Toshikazu Kondou , Yukihiro Hiraishi , Kunio Kishimoto
IPC分类号： B05D5/12 , B05D3/12
CPC分类号： H05K3/4069 , H05K2201/0355 , H05K2201/09036 , H05K2201/09781 , H05K2203/0191 , H05K2203/0228 , H05K2203/063 , H05K2203/1461
摘要： A mask film, where squeegee cleaning part has been formed at a predetermined position, and another mask film are attached to both sides of a substrate. A through-hole is formed by using a laser, and conductive paste is filled into the through-hole by using a squeezing method. As discussed above, a paste-residue can be prevented on the through-hole, so that a circuit board having high quality of connection can be obtained.
摘要翻译：已经在预定位置形成刮板清洁部分的掩模膜，并且另一个掩模膜附着到基板的两侧。通过使用激光形成通孔，并且通过使用挤压方法将导电膏填充到通孔中。如上所述，可以在通孔上防止糊料残留，从而可以获得具有高连接质量的电路板。

2. 发明授权

US07066344B2 Mask film, its manufacturing method, and manufacturing method of circuit board using the same 失效
公开(公告)号：US07066344B2
公开(公告)日：2006-06-27
申请号：US10338642
申请日：2003-01-09
申请人： Toshiaki Takenaka , Toshikazu Kondo , Kunio Kishimoto , Shinji Nakamura , Fumio Echigo
发明人： Toshiaki Takenaka , Toshikazu Kondo , Kunio Kishimoto , Shinji Nakamura , Fumio Echigo
IPC分类号： H01B13/00
CPC分类号： H05K3/4069 , H05K2201/0355 , H05K2203/0191 , H05K2203/0522 , H05K2203/1461 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155
摘要： A mask film includes a base material, a parting layer and a non-parting portion placed on the base material. Accordingly, an optimum adhesion strength of the mask film and a prepreg sheet can be maintained, and peeling between the mask film and prepreg sheet can be prevented. Further, by preventing the fusing adhesion between the mask film and prepreg sheet due to heat generated when forming penetration holes, a circuit board having an excellent quality is obtained.

3. 发明授权

US06890449B2 Method for manufacturing printed-circuit board 失效
标题翻译：印刷电路板制造方法
公开(公告)号：US06890449B2
公开(公告)日：2005-05-10
申请号：US10048927
申请日：2001-06-05
申请人： Eiji Kawamoto , Shigeru Yamane , Toshiaki Takenaka , Toshihiro Nishii
发明人： Eiji Kawamoto , Shigeru Yamane , Toshiaki Takenaka , Toshihiro Nishii
IPC分类号： H05K1/11 , H05K3/00 , H05K3/40 , H01K13/00 , H05K3/36
CPC分类号： H05K3/4069 , H05K2201/0355 , H05K2201/09827 , H05K2201/09845 , H05K2203/0191 , H05K2203/1461 , Y10T29/49126
摘要： A method of manufacturing a PCB comprising the steps of: forming through-holes in a substrate having releasing layers on front and back faces; filling conductive paste in the through-holes; removing the releasing layers and disposing metal foil on both faces of the substrate; and heat pressing them. A diameter of the through-holes is larger than that of corresponding holes formed on the releasing layers. According to the present invention, when the conductive paste is compressed, conductive paste protruding from the surface of the substrate is trapped at the edges of the through-holes. This configuration prevents short circuits with undesirable wiring patterns. So, an enough amount of the conductive paste can protrude from the surface of the substrate. Therefore, after the compression, stable electric connections inside the conductive paste and between the conductive paste and the metal foils are ensured, thus PCBs with superior reliability can be produced.
摘要翻译：一种制造PCB的方法，包括以下步骤：在前面和背面上形成具有释放层的衬底中的通孔; 在通孔中填充导电膏; 去除释放层并在金属箔的两个面上设置金属箔; 并热压它们。通孔的直径大于形成在释放层上的相应孔的直径。根据本发明，当导电膏被压缩时，从基板的表面突出的导电糊被截留在通孔的边缘。这种配置可以防止出现不良布线图形的短路。因此，足够量的导电膏可以从基板的表面突出。因此，在压缩之后，确保导电浆料内部和导电性糊料与金属箔之间的稳定的电连接，从而可以制造出具有高可靠性的PCB。

4. 发明授权

US06820331B2 Method of manufacturing a circuit board and its manufacturing apparatus 失效
标题翻译：制造电路板及其制造装置的方法
公开(公告)号：US06820331B2
公开(公告)日：2004-11-23
申请号：US09736499
申请日：2000-12-15
申请人： Kunio Kishimoto , Toshihiro Nishii , Toshiaki Takenaka , Shinji Nakamura , Akihiro Miura
发明人： Kunio Kishimoto , Toshihiro Nishii , Toshiaki Takenaka , Shinji Nakamura , Akihiro Miura
IPC分类号： H01K310
CPC分类号： H05K3/4069 , H05K3/0032 , H05K3/0055 , H05K3/0088 , H05K2201/0355 , H05K2203/0191 , H05K2203/0257 , H05K2203/0285 , H05K2203/0786 , H05K2203/081 , H05K2203/1461 , Y10S134/902 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , Y10T428/13
摘要： It is possible to obtain a clean high-quality circuit board by removing affected material and foreign matter produced when a hole is formed. A manufacturing method of the circuit board includes (a) preparing a film-coated board material by bonding a film material as a mask to a board material, (b) forming a hole in the film-coated board material by applying a laser beam thereto, and (c) selectively removing the unnecessary material sticking to the film-coated board material from the film-coated board material by supersonic cleaning without peeling the film material off the board material. Unnecessary material such as foreign matter is produced when the hole is formed, and the unnecessary material sticks to the board material. After removal of such unnecessary material, a conductive material is disposed in the hole, using the film material as a mask, and the film material is later removed from the board material.
摘要翻译：通过去除受影响的材料和形成孔时产生的异物，可以获得清洁的高质量电路板。电路基板的制造方法包括：（a）通过将作为掩模的膜材料粘合到基板材料上来制备薄膜基板材料，（b）通过向其施加激光而在薄膜基板材料上形成孔，（c）通过超声波清洗，不从膜材剥离薄膜材料，从薄膜基板材料上选择性除去粘附在薄膜基板材料上的不必要的材料。当形成孔时产生诸如异物等不必要的材料，并且不需要的材料粘附到基板材料上。在去除这种不必要的材料之后，使用膜材料作为掩模将导电材料设置在孔中，并且膜材料随后从基板材料中去除。

5. 发明申请

US20080251193A1 Method of Manufacturing Multi-Layer Circuit Board 失效
标题翻译：多层电路板制造方法
公开(公告)号：US20080251193A1
公开(公告)日：2008-10-16
申请号：US10595157
申请日：2005-09-30
申请人： Toshiaki Takenaka , Yoshihiro Kawakita , Tadashi Tojyo , Yuichiro Sugita
发明人： Toshiaki Takenaka , Yoshihiro Kawakita , Tadashi Tojyo , Yuichiro Sugita
IPC分类号： B32B37/14
CPC分类号： H05K3/4652 , H05K3/4069 , H05K3/4614 , H05K2201/0355 , H05K2201/068 , H05K2203/068 , Y10T29/49126
摘要： A method of manufacturing a multi-layer circuit board having the following steps: preparing a laminated member formed of a core circuit board having a circuit pattern thereon and a prepreg sheet having a through-hole filled with conductive paste; forming a laminated structure in a manner that the laminated member is sandwiched by lamination plates; and applying heat and pressure to the laminated structure. According to the method, selecting a lamination plate so as to have thermal expansion coefficient equivalent to that of a core circuit board can protect conductive paste from distortion, thereby offering a high-quality multi-layer circuit board with reliable connection resistance.
摘要翻译：一种制造多层电路板的方法，具有以下步骤：制备由其上具有电路图案的芯线电路板形成的层压件和具有填充有导电浆料的通孔的预浸料片; 以叠层构件夹持层压板的方式形成层压结构; 并向叠层结构施加热和压力。根据该方法，选择层压板以使其具有与芯电路板的热膨胀系数相当的热膨胀系数可以保护导电膏不发生变形，从而提供具有可靠连接电阻的高品质多层电路板。

6. 发明申请

US20050144780A1 Method for manufacturing substrate, release sheet, substrate manufacturing apparatus and method for manufacturing substrate using same 审中-公开
标题翻译：制造基板，剥离片，基板制造装置的方法以及使用其的基板的制造方法
公开(公告)号：US20050144780A1
公开(公告)日：2005-07-07
申请号：US10509754
申请日：2004-01-19
申请人： Kunio Hishimoto , Toshiaki Takenaka , Yukihiro Hiraishi
发明人： Kunio Hishimoto , Toshiaki Takenaka , Yukihiro Hiraishi
IPC分类号： B29C70/46 , C08J5/24 , H05K3/02 , H05K3/40 , H05K3/46 , B65B1/00 , H05K3/20 , B29C33/68 , B29C41/42 , B32B31/20
CPC分类号： B29C70/46 , B29L2031/3425 , B32B37/26 , B32B2037/268 , B32B2305/08 , B32B2311/12 , B32B2398/10 , B32B2457/08 , C08J5/24 , H05K3/022 , H05K3/4069 , H05K3/4611 , H05K3/4614 , H05K3/4638 , H05K3/4652 , H05K3/4679 , H05K2201/0355 , H05K2203/0195 , H05K2203/0264 , H05K2203/065 , H05K2203/068 , Y10T29/49126 , Y10T29/49128 , Y10T156/16 , Y10T156/1712 , Y10T428/31
摘要： A highly reliable and productive manufacturing method of boards and a manufacturing apparatus are provided. The manufacturing apparatus includes heater-punches (4a) and (4b) disposed above and under pressuring holes (24) provided on positioning stage (6) which positions and laminates board materials. The apparatus also includes a supplying and discharging means of a mold-releasing sheet, and the means is formed of supply reel (22), take-up reel (23), and guide rolls (25a) and (25b). The sheet is supplied and discharged passing between heater-punches (4a) placed above pressuring holes (24) and heater-punches (4b) placed under pressuring holes (24).
摘要翻译：提供了一种高可靠性高的制造方法和制造装置。制造装置包括设置在定位台（6）上的加压孔（24）的上方和下方的加热器冲头（4a）和（4b），所述加压孔位于并叠置板材料。该设备还包括一个脱模片的供应和排出装置，该装置由供给卷轴（22），卷取卷轴（23）和导向辊（25a）和（25b）构成。通过放置在加压孔（24）之间的加热器冲头（4a）和加压孔（24）之间的加热器冲头（4b）之间的供给和排出。

7. 发明申请

US20050006139A1 Circuit board and process for producing the same 有权
标题翻译：电路板及其制造方法
公开(公告)号：US20050006139A1
公开(公告)日：2005-01-13
申请号：US10502170
申请日：2003-12-26
申请人： Toshiaki Takenaka , Yoshihiro Kawakita , Tadashi Tojo , Kiyohide Tatsumi
发明人： Toshiaki Takenaka , Yoshihiro Kawakita , Tadashi Tojo , Kiyohide Tatsumi
IPC分类号： H05K3/40 , H05K3/46 , H05K1/09 , H05K3/20
CPC分类号： H05K3/4069 , H05K3/4614 , H05K3/4652 , H05K2201/0355 , H05K2203/068 , H05K2203/1461 , H05K2203/1476 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165
摘要： After disposing metallic foils on either surface of a prepreg sheet of low compressibility having conducting holes filled with conductive paste, the prepreg sheet is compressed in a state of being kept at a relatively low temperature, and after that, the temperature is raised under pressure to melt and harden the resin in the prepreg sheet, and thereby, the connecting resistance is stabilized, and a high-quality circuit board can be obtained.
摘要翻译：在具有填充有导电膏的导电孔的具有低压缩性的预浸料片的任一表面上设置金属箔之后，在保持在较低温度的状态下将预浸料片压缩，之后将温度在压力下升高至熔融并硬化预浸料片中的树脂，从而使连接电阻稳定，并且可以获得高质量的电路板。

8. 发明授权

US06700071B2 Multi-layer circuit board having at least two or more circuit patterns connected 失效
标题翻译：具有连接至少两个或更多个电路图案的多层电路板
公开(公告)号：US06700071B2
公开(公告)日：2004-03-02
申请号：US09928966
申请日：2001-08-14
申请人： Toshiaki Takenaka , Toshihiro Nishii , Shigeru Yamane , Shinji Nakamura , Hideaki Komoda , Kunio Kishimoto
发明人： Toshiaki Takenaka , Toshihiro Nishii , Shigeru Yamane , Shinji Nakamura , Hideaki Komoda , Kunio Kishimoto
IPC分类号： H05K103
CPC分类号： H05K3/462 , H05K1/0268 , H05K3/386 , H05K3/4069 , H05K3/4652 , H05K2201/0195 , H05K2201/0355 , H05K2201/10378 , H05K2203/0191 , H05K2203/066 , H05K2203/1461 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A circuit board having stable connection resistance can be obtained . The multi-layer circuit board includes the steps of making through-holes in a incompressible substrate having films on either side thereof via a bonding layer; filling conductive paste into the through-holes; removing the films from the substrate; laminating metallic foils to either side of the substrate and heating same under pressures to harden the bonding layer, bonding the metallic foils to the substrate and electrically connecting the sides of the substrate to each other; and forming a circuit pattern by machining the metallic foils.
摘要翻译：可以获得具有稳定的连接电阻的电路板。多层电路板包括以下步骤：在不可压缩的基板上形成通孔，该基板在其任一侧经由接合层具有膜; 将导电膏填充到通孔中; 从基板去除膜; 将金属箔层叠到基板的任一侧并在压力下加热相同以使粘合层硬化，将金属箔粘合到基板上并将基板的侧面彼此电连接; 并通过加工金属箔形成电路图案。

9. 发明授权

US06528733B2 Multi-layer circuit board and method of manufacturing same 失效
公开(公告)号：US06528733B2
公开(公告)日：2003-03-04
申请号：US09902800
申请日：2001-07-12
申请人： Toshiaki Takenaka , Toshihiro Nishii , Shigeru Yamane , Shinji Nakamura , Hideaki Komoda , Kunio Kishimoto
发明人： Toshiaki Takenaka , Toshihiro Nishii , Shigeru Yamane , Shinji Nakamura , Hideaki Komoda , Kunio Kishimoto
IPC分类号： H05K103
CPC分类号： H05K3/4614 , H05K3/4069 , H05K3/4652 , H05K2201/0195 , H05K2201/0355 , H05K2201/10378 , H05K2203/1461 , Y10T29/49126 , Y10T29/49155
摘要： An inner layer circuit board with a convex inner layer circuit pattern having a predetermined thickness, a prepreg sheet having conductive material disposed in a plurality of through-holes and metallic foil are laminated to a substrate, and the laminated board is heated under pressures. After that, a laminated circuit pattern is formed by machining the metallic foil. In such multi-layer circuit board, a smoothing layer is disposed on a concave portion where no inner layer circuit pattern of the inner layer circuit board is formed. In this way, the conductive materials disposed in a plurality of through-holes are uniformly compressed. As a result, the connection resistance between the inner circuit pattern and the laminated circuit pattern becomes stabilized.

10. 发明授权

US06523258B2 Method of manufacturing printed circuit board 失效
标题翻译：制造印刷电路板的方法
公开(公告)号：US06523258B2
公开(公告)日：2003-02-25
申请号：US09799812
申请日：2001-03-07
申请人： Eiji Kawamoto , Shigeru Yamane , Toshiaki Takenaka
发明人： Eiji Kawamoto , Shigeru Yamane , Toshiaki Takenaka
IPC分类号： H05K302
CPC分类号： H05K3/4069 , H05K3/0032 , H05K2201/0355 , H05K2203/0191 , H05K2203/1461 , Y10T29/49117 , Y10T29/49155 , Y10T29/49156 , Y10T29/49163 , Y10T29/49165
摘要： A method of performing a printed circuit board including the steps of: (a) disposing a first release film on the surface of a substrate and a second release film on the back of the substrate; (b) forming a through-hole in the first release film, the second release film, and the substrate; (c) filling conductive paste into a through-hole; (d) removing the first release film and the second release film from the substrate with the through-hole filled with the conductive paste; (e) placing a first metallic member on the surface of the substrate with the release films removed and placing a second metallic member on the back of the substrate; (f) compressing under heat the substrate with the first metallic member and the second metallic member disposed thereon; and (g) forming a desired circuit pattern on the first metallic member and the second metallic member.
摘要翻译：一种执行印刷电路板的方法，包括以下步骤：（a）在基板的表面上设置第一剥离膜和在基板的背面设置第二剥离膜; （b）在第一脱模膜，第二剥离膜和基材中形成通孔; （c）将导电膏填充到通孔中; （d）使填充有导电糊的通孔从基板上除去第一剥离膜和第二剥离膜; （e）将第一金属构件放置在基板的表面上，同时移除释放膜并将第二金属构件放置在基板的背面上; （f）在第一金属构件和设置在其上的第二金属构件的基板上加热压缩; 和（g）在第一金属构件和第二金属构件上形成期望的电路图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式