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1. 发明授权

US07870466B2 Parallel cyclic code generation device and parallel cyclic code error detection device 有权
标题翻译：并行循环码生成装置和并行循环码错误检测装置
公开(公告)号：US07870466B2
公开(公告)日：2011-01-11
申请号：US12198389
申请日：2008-08-26
申请人： Masahiro Shigihara , Toru Takamichi
发明人： Masahiro Shigihara , Toru Takamichi
IPC分类号： H03M13/00
CPC分类号： H03M13/091
摘要： To eliminate the need for buffering in order to calculate data length information on data as an object of computation, a first exclusive-OR unit 53 executes computation of exclusive-OR of a cyclic code R(x) of the integral multiple bit bits block A(x) and a data string of M bits, containing the fraction bits block B(x). A first shifting unit 54 shifts the exclusive-OR of the cyclic code R(x) and the data string of M bits, containing the fraction bits block B(x), by {M−H(k)} bits toward a least significant side, where M is a parallel width and H(k) is a bit length of the fraction bits block B(x). An R′(x) generation unit 55 generates a cyclic code R′(x) that is a cyclic code of the data after shifting. To obtain R″(x), a second shifting unit 56 shifts the cyclic code R(x) by H(k) bits toward a most significant side. A second exclusive-OR unit 57 executes computation of exclusive-OR of the cyclic code R′(x) and data R″(x).
摘要翻译：为了消除对缓冲的需要，为了计算关于作为计算对象的数据的数据长度信息，第一异或单元53执行积分多位比特块A的循环码R（x）的异或运算（x）和包含分数位块B（x）的M位数据串。第一移位单元54将包含分数比特块B（x）的循环码R（x）和包含分数比特块B（x）的M比特数据串的异或移位为最小有效值{M-H（k）} 侧，其中M是并行宽度，H（k）是分数比特块B（x）的比特长度。 R'（x）生成单元55生成作为移位后的数据的循环码的循环码R'（x）。为了获得R“（x），第二移位单元56将循环码R（x）移位H（k）比特朝向最重要的一侧。第二异或单元57执行循环码R'（x）和数据R“（x）的异或运算。

2. 发明授权

US06084857A Cell rate supervising apparatus 失效
标题翻译：单元速率监控装置
公开(公告)号：US06084857A
公开(公告)日：2000-07-04
申请号：US916162
申请日：1997-08-21
申请人： Toru Takamichi
发明人： Toru Takamichi
IPC分类号： H04Q3/00 , H04L12/813 , H04Q11/04 , G01R31/08 , G06F11/00 , G08C15/00
CPC分类号： H04L12/5602 , H04L49/105 , H04Q11/0478 , H04L2012/5615 , H04L2012/5616 , H04L2012/5636
摘要： A BRM changing circuit 4 that changes congestion information of a BRM cell is disposed on the output side of a down line (from the network side to the user side) of a cell rate supervising apparatus. The BRM changing circuit 4 places an ACR value calculated by an ACR calculating circuit 3 with congestion information (a CI bit, an NI bit, and an ER area) in a BRM cell received from the network through the down line to the ER area of the BRM cell. The resultant BRM cell that has been changed by the BRM changing circuit 4 is sent to the user side terminal unit through the down line.
摘要翻译：改变BRM单元的拥塞信息的BRM改变电路4设置在单元速率监视装置的下行（从网络侧到用户侧）的输出侧。 BRM改变电路4将ACR计算电路3计算出的ACR值在从网络通过下行线路接收到的BRM小区中具有拥塞信息（CI比特，NI比特和ER区域）到ER区域 BRM细胞。通过BRM改变电路4改变的结果BRM单元通过下行线路发送到用户侧终端单元。

3. 发明申请

US20120027020A1 MULTIPLEXING TRANSMISSION SYSTEM, MULTIPLEXING APPARATUS, DEMULTIPLEXING APPARATUS AND A MULTIPLEXING TRANSMISSION SYSTEM 有权
标题翻译：多路复用传输系统，多路复用装置，复用装置和多路传输系统
公开(公告)号：US20120027020A1
公开(公告)日：2012-02-02
申请号：US13260273
申请日：2010-03-26
申请人： Masahiro Shigihara , Toru Takamichi
发明人： Masahiro Shigihara , Toru Takamichi
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04J3/1682
摘要： A multiplexing apparatus stores fixed length data into which information signals supplied from channels are divided; determines an output channel by selecting the each channel cyclically; and acquires the fixed length data from the output channel based on a channel multiplexing ratio number to store the fixed length data in a payload in turn. Also, the multiplexing apparatus adds assignment information, which includes a channel arrangement of each channel of the fixed length data stored in the payload, to the payload. Further, the multiplexing apparatus creates a multiplexing frame by using the payload to transmit to a transmission channel. A demultiplexing apparatus detects the assignment information from the payload of the multiplexing frame received to the transmission channel; and creates distribution information for distributing the fixed length data to each channel based on the assignment information. Also, the demultiplexing apparatus detects the fixed length data from the payload to distribute the fixed length data to each channel based on the distribution information. Further, the demultiplexing apparatus couples the fixed length data to reproduce the information signal.
摘要翻译：多路复用装置存储从信道提供的信息信号被划分成的固定长度数据; 通过循环选择每个通道来确定输出通道; 并且基于信道复用率数字从输出信道获取固定长度数据，以将固定长度数据依次存储在有效负载中。此外，多路复用装置将存储在有效载荷中的固定长度数据的每个信道的信道排列的分配信息添加到有效载荷中。此外，复用装置通过使用有效载荷来发送到传输信道来创建多路复用帧。解复用装置从接收到传输信道的复用帧的有效载荷中检测分配信息; 并且基于分配信息创建用于将固定长度数据分发到每个信道的分发信息。此外，解复用装置从有效载荷检测固定长度数据，以便根据分发信息将固定长度数据分配给每个信道。此外，解复用装置耦合固定长度数据以再现信息信号。

4. 发明授权

US07359331B2 Alarm transfer method and wide area Ethernet network 有权
标题翻译：报警传输方式和广域以太网
公开(公告)号：US07359331B2
公开(公告)日：2008-04-15
申请号：US10784875
申请日：2004-02-24
申请人： Toru Takamichi
发明人： Toru Takamichi
IPC分类号： H04L12/26
CPC分类号： H04L45/28 , H04L41/06 , H04L45/22
摘要： An alarm transfer method for use in a wide area Ethernet network has the steps of generating a plurality of fixed-length frames from an Ethernet frame sent from a client terminal, generating capsules each comprised of each of the fixed-length frames, a type field for notifying a fault, a forward relay line fault notification field for notifying a fault in a forward direction, and a backward relay line fault notification field for notifying the fault in a backward direction, multiplexing the capsules to generate a frame which is transferred to an Ethernet network, and demultiplexing capsules from a received frame to recognize a fault for each Ethernet path.
摘要翻译：在广域以太网网络中使用的报警传送方法具有以下步骤：从客户终端发送的以太网帧生成多个固定长度帧，生成由每个固定长度帧组成的盒，一个类型字段用于通知故障，用于通知正向故障的前向中继线故障通知字段和用于向后方向通知故障的后向中继线故障通知字段，复用该胶囊以生成被转移到以太网网络，以及从接收到的帧解复用胶囊，以识别每个以太网路径的故障。

5. 发明授权

US6072776A Fault self-supervising system of cell processor 失效
标题翻译：单元处理器故障自监控系统
公开(公告)号：US6072776A
公开(公告)日：2000-06-06
申请号：US795804
申请日：1997-02-05
申请人： Toru Takamichi
发明人： Toru Takamichi
IPC分类号： H04Q3/00 , H04L12/70 , H04Q11/04 , G06F11/00
CPC分类号： H04Q11/0478 , H04L2012/5627 , H04L2012/5652
摘要： There is provided a fault self-supervising system of cell processor to execute fault supervising for internal circuit in the cell processor during the in-service period while the ordinary operation of the cell processor is kept without giving any influence on the main signal cell flow in the cell processor of the ATM network. In the structure of the fault self-supervising system of cell processor, the cell such as control cell or idle cell in the ATM cell flow which is not processed in the cell processor is overwritten by the supervising cell having a combination of VPI and VCI which is not used in the cell process and it is then applied in the preceding stage of the arithmetic circuit as the supervising object an is then transferred within the arithmetic circuit, the supervising information signal CHK indicating the operating condition of the arithmetic circuit obtained as a result of the transfer is compared and collated with the expected value E, a defective circuit of arithmetic circuit is detected from matching/mismatching as a result of comparison and the supervising cell is extracted in the subsequent stage of the arithmetic circuit.
摘要翻译：提供了一种单元处理器的故障自监控系统，用于在使用期内对单元处理器的内部电路执行故障监控，同时保持单元处理器的常规操作，而不会对主信号单元流动产生任何影响 ATM网络的小区处理器。在小区处理器的故障自监控系统的结构中，在具有VPI和VCI的组合的监控小区中覆盖在小区处理器中未处理的ATM信元流中的控制小区或空闲小区等小区被覆盖，在运算电路中，当在运算电路中传输监视对象an时，在运算电路的前级中不使用该运算电路，由此得到运算电路的运行状态的监视信息信号CHK 将该传送与期望值E进行比较并整理，作为比较的结果，从匹配/失配检测运算电路的缺陷电路，并且在运算电路的后续级中提取监视单元。

6. 发明申请

US20100070839A1 CYCLIC CODE PROCESSING CIRCUIT, NETWORK INTERFACE CARD, AND CYCLIC CODE PROCESSING METHOD 有权
标题翻译：循环码处理电路，网络接口卡和循环码处理方法
公开(公告)号：US20100070839A1
公开(公告)日：2010-03-18
申请号：US12557269
申请日：2009-09-10
申请人： Masahiro SHIGIHARA , Toru TAKAMICHI
发明人： Masahiro SHIGIHARA , Toru TAKAMICHI
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/091 , H04L1/0052 , H04L1/0061
摘要： Processor 23 calculates a first remainder, which is a remainder produced when an integral multiple data block is divided by a generator poly-nomial, by processing bits represented by the number of parallel bits in parallel. The integral multiple data block comprises bits positioned closer to the leading end of the input data than a final word which is a word at the tail end of the input data, in the case where a plurality of bits making up the input data are successively divided from the leading end with respect to each word which comprises the bits represented by the number of parallel bits. Processor 23 calculates a second remainder, which is a remainder produced when a final word valid data block made up of bits of the input data other than the integral multiple data block is divided by the generator polynomial. Processor 23 calculates an input data remainder, which is a remainder produced when the input data are divided by the generator polynomial, based on the first remainder and the second remainder.
摘要翻译：处理器23通过处理由并行比特数并行表示的位来计算第一余数，其是当整数多个数据块被发生器多项式分割时产生的余数。在构成输入数据的多个比特被连续分割的情况下，整数多个数据块包括比输入数据的尾端更靠近输入数据的前端的比比作为输入数据的尾端的字的最后一个字从包括由并行比特数表示的比特的每个单词的前端开始。处理器23计算第二余数，其是当由整数多个数据块以外的输入数据的位组成的最终字有效数据块除以生成多项式时产生的余数。处理器23基于第一余数和第二余数计算输入数据余数，该输入数据余数是当输入数据被生成多项式除以时产生的余数。

7. 发明授权

US06615388B1 Low power path memory for viterbi decoders 失效
标题翻译：用于维特比解码器的低功率路径存储器
公开(公告)号：US06615388B1
公开(公告)日：2003-09-02
申请号：US09654331
申请日：2000-09-01
申请人： Toru Takamichi
发明人： Toru Takamichi
IPC分类号： H03M1300
CPC分类号： H03M13/6502 , H03M13/4107
摘要： A path memory for a Viterbi decoder stores 2k−1 path select command signals generated a T interval earlier than reference clock timing. In response to a path select command signal that is generated at the reference clock timing corresponding to each of the 2k−1 rows, one of the stored path select command signals which correspond to two possible states of a 2T interval earlier than the reference clock timing and are separated from each other by a distance of 2k−2 rows, is selected for each row. A matrix array of memory cells are arranged in the 2k−1 rows. To achieve low power consumption, the memory, cells are divided into a first array of odd-numbered columns and a second array of even-numbered columns. Each row of the first-array memory cells is responsive to the row-corresponding path select command signal and the selected path select command signal for selecting one of four possible states latched in the memory cells of preceding odd-numbered columns a 2T interval earlier than the reference clock timing, and each row of the second-array memory cells is responsive to the row-corresponding path select command signal and the selected path select command signal for selecting one of four possible states latched in the memory cells of preceding even-numbered columns a 2T interval earlier than the reference clock timing. The first and second arrays alternately operate at 2T-intervals.
摘要翻译：用于维特比解码器的路径存储器存储比参考时钟定时早产生T间隔的2k-1路径选择命令信号。响应于在对应于2k-1行中的每一个的参考时钟定时产生的路径选择命令信号，存储的路径选择命令信号中的一个对应于早于参考时钟定时的2T间隔的两个可能状态并且为每行选择2k-2行的距离。存储器单元的矩阵阵列被布置在2k-1行中。为了实现低功耗，存储器单元被分成奇数列的第一阵列和偶数列的第二阵列。第一阵列存储单元的每行响应于行对应的路径选择命令信号和所选择的路径选择命令信号，用于选择锁存在先前奇数列的存储单元中的四个可能状态之一a 2T间隔参考时钟定时和第二阵列存储单元的每一行响应于行对应的路径选择命令信号和所选择的路径选择命令信号，用于选择锁存在先前偶数编号的存储单元中的四种可能状态之一列比参考时钟时钟早2T间隔。第一和第二阵列交替地以2T间隔操作。

8. 发明授权

US5974033A Dynamic shaping apparatus of traffic of ATM network 失效
标题翻译： ATM网络流量动态整形设备
公开(公告)号：US5974033A
公开(公告)日：1999-10-26
申请号：US815400
申请日：1997-03-10
申请人： Satoshi Kamiya , Toru Takamichi , Tutomu Murase
发明人： Satoshi Kamiya , Toru Takamichi , Tutomu Murase
IPC分类号： H04Q3/00 , H04L12/815 , H04L12/863 , H04Q11/04 , H04L12/24 , H04L12/56
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5635 , H04L2012/5679 , H04L2012/568
摘要： The invention provides a dynamic traffic shaping apparatus which allows dynamic shaping processing wherein the shaping cell rate is varied dynamically in response to a rate variation of a terminal acquired from a network. The dynamic traffic shaping apparatus includes a rate information processing section for predicting a sending rate of a transmission terminal in response to rate control information detected from a cell directed from a reception terminal side toward a transmission terminal side and successively storing the sending rate in an updating manner as sending rate information of an arrival cell for each virtual path and each virtual channel. The cell stored in a cell buffer for temporarily storing an arrival cell arriving from the transmission terminal side for each virtual path and each virtual channel is read out at an interval based on the sending rate information stored in the rate information processing section corresponding to the virtual path and the virtual channel and is sent out to the reception terminal side by a read control section.
摘要翻译：本发明提供了一种动态流量整形装置，其允许动态整形处理，其中整形信元速率响应于从网络获得的终端的速率变化而动态变化。动态流量整形装置包括速率信息处理部分，用于响应从从接收终端侧朝向发送终端侧检测到的小区的速率控制信息来预测发送终端的发送速率，并且将发送速率连续地存储在更新作为每个虚拟路径和每个虚拟通道的到达单元的发送速率信息。存储在单元缓冲器中的用于每个虚拟路径和每个虚拟通道临时存储从传输终端侧到达的到达单元的单元基于存储在与虚拟的对应的速率信息处理部分中的发送速率信息以一定间隔被读出路径和虚拟信道，并通过读取控制部分发送到接收终端侧。

9. 发明授权

US08402353B2 Cyclic code processing circuit, network interface card, and cyclic code processing method 有权
标题翻译：循环码处理电路，网络接口卡和循环码处理方法
公开(公告)号：US08402353B2
公开(公告)日：2013-03-19
申请号：US12557269
申请日：2009-09-10
申请人： Masahiro Shigihara , Toru Takamichi
发明人： Masahiro Shigihara , Toru Takamichi
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： H03M13/091 , H04L1/0052 , H04L1/0061
摘要： A cyclic code processing circuit, network interface card, and method for calculating a remainder from input data comprising a plurality of bits arranged in parallel. The calculation is performed by first computing a first remainder obtained by dividing an integral multiple data block by a generator polynomial, the integral multiple data block comprising a plurality of words that precede the final word of the input data. Then, a second remainder is computed by dividing the final word by the generator polynomial, the final word comprising the parallel bits located at the end of the input data. The input data remainder is calculated using the first and the second previously calculated remainders.
摘要翻译：循环码处理电路，网络接口卡和用于从包括并行布置的多个比特的输入数据计算余数的方法。通过首先计算通过将整数多个数据块除以生成多项式获得的第一余数来执行计算，所述积分多数据块包括在输入数据的最终字之前的多个字。然后，通过将最终字除以生成多项式来计算第二个余数，最后一个字包括位于输入数据末尾的并行位。使用第一和第二预先计算的余数来计算输入数据余数。

10. 发明申请

US20090106631A1 PARALLEL CYCLIC CODE GENERATION DEVICE AND PARALLEL CYCLIC CODE ERROR DETECTION DEVICE 有权
标题翻译：并行循环码生成装置和并行循环码错误检测装置
公开(公告)号：US20090106631A1
公开(公告)日：2009-04-23
申请号：US12198389
申请日：2008-08-26
申请人： MASAHIRO SHIGIHARA , Toru TAKAMICHI
发明人： MASAHIRO SHIGIHARA , Toru TAKAMICHI
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/091
摘要： To eliminate the need for buffering in order to calculate data length information on data as an object of computation, a first exclusive-OR unit 53 executes computation of exclusive-OR of a cyclic code R(x) of the integral multiple bit bits block A(x) and a data string of M bits, containing the fraction bits block B(x). A first shifting unit 54 shifts the exclusive-OR of the cyclic code R(x) and the data string of M bits, containing the fraction bits block B(x), by {M−H(k)} bits toward a least significant side, where M is a parallel width and H(k) is a bit length of the fraction bits block B(x). An R′(x) generation unit 55 generates a cyclic code R′(x) that is a cyclic code of the data after shifting. To obtain R″(x), a second shifting unit 56 shifts the cyclic code R(x) by H(k) bits toward a most significant side. A second exclusive-OR unit 57 executes computation of exclusive-OR of the cyclic code R′(x) and data R″(x).
摘要翻译：为了消除对缓冲的需要，为了计算关于作为计算对象的数据的数据长度信息，第一异或单元53执行积分多位比特块A的循环码R（x）的异或运算（x）和包含分数位块B（x）的M位数据串。第一移位单元54将包含分数比特块B（x）的循环码R（x）和M比特数据串的异或向最不重要侧移位{MH（k）}比特，其中M是并行宽度，H（k）是分数比特块B（x）的比特长度。 R'（x）生成单元55生成作为移位后的数据的循环码的循环码R'（x）。为了获得R“（x），第二移位单元56将循环码R（x）向最显着侧移位H（k）位。第二异或单元57执行循环码R'（x）和数据R“（x）的异或运算。

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