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1. 发明授权

US09000447B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US09000447B2
公开(公告)日：2015-04-07
申请号：US13613838
申请日：2012-09-13
申请人： Keiji Wada , Takeyoshi Masuda , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Toru Hiyoshi
IPC分类号： H01L29/15 , H01L21/04 , H01L29/66 , H01L29/04 , H01L29/78 , H01L29/16 , H01L29/423 , H01L29/06
CPC分类号： H01L21/0475 , H01L21/049 , H01L29/045 , H01L29/0623 , H01L29/1608 , H01L29/36 , H01L29/4236 , H01L29/66068 , H01L29/7813
摘要： A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1≦ND/NA≦50 is satisfied is within 1 μm therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.
摘要翻译：第一层具有n型导电性。第二层外延形成在第一层上并具有p型导电性。第三层位于第二层上，具有n型导电性。 ND被定义为表示供体型杂质的浓度。 NA被定义为表示受体型杂质的浓度。 D1被定义为在深度方向上表示远离第一层和第二层之间的界面的第一层中的位置。其中满足1＆nlE; ND / NA＆nlE; 50的D1在其1μm以内。提供栅极沟槽以延伸穿过第三层和第二层以到达第一层。栅极绝缘膜覆盖栅极沟槽的侧壁。栅极电极嵌入栅极沟槽中，栅极绝缘膜插入其间。

2. 发明申请

US20130078771A1 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US20130078771A1
公开(公告)日：2013-03-28
申请号：US13613858
申请日：2012-09-13
申请人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
发明人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
IPC分类号： H01L21/331
CPC分类号： H01L29/66068 , H01L29/1608 , H01L29/7395
摘要： A collector layer having p type is formed on a silicon carbide substrate having n type. A drift layer having n type is formed on a top surface side of the collector layer. A body region provided on the drift layer and having p type, and an emitter region provided on the body region to be separated from the drift layer by the body region and having n type are formed. A bottom surface side of the collector layer is exposed by removing the silicon carbide substrate.
摘要翻译：具有p型的集电极层形成在具有n型的碳化硅衬底上。在集电体层的顶面侧形成有n型漂移层。设置在漂移层上并具有p型的体区，并且形成设置在身体区域上以通过身体区域与移动层分离并具有n型的发射极区域。通过去除碳化硅衬底来暴露集电极层的底表面侧。

3. 发明申请

US20130075759A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：US20130075759A1
公开(公告)日：2013-03-28
申请号：US13613838
申请日：2012-09-13
申请人： Keiji Wada , Takeyoshi Masuda , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Toru Hiyoshi
IPC分类号： H01L29/161
CPC分类号： H01L21/0475 , H01L21/049 , H01L29/045 , H01L29/0623 , H01L29/1608 , H01L29/36 , H01L29/4236 , H01L29/66068 , H01L29/7813
摘要： A first layer has n type conductivity. A second layer is epitaxially formed on the first layer and having p type conductivity. A third layer is on the second layer and having n type conductivity. ND is defined to represent a concentration of a donor type impurity. NA is defined to represent a concentration of an acceptor type impurity. D1 is defined to represent a location in the first layer away from an interface between the first layer and the second layer in a depth direction. D1 in which 1≦ND/NA≦50 is satisfied is within 1 μm therefrom. A gate trench is provided to extend through the third layer and the second layer to reach the first layer. A gate insulating film covers a side wall of the gate trench. A gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween.
摘要翻译：第一层具有n型导电性。第二层外延形成在第一层上并具有p型导电性。第三层位于第二层上，具有n型导电性。 ND被定义为表示供体型杂质的浓度。 NA被定义为表示受体型杂质的浓度。 D1被定义为在深度方向上表示远离第一层和第二层之间的界面的第一层中的位置。其中满足1＆nlE; ND / NA＆nlE; 50的D1在其1μm以内。提供栅极沟槽以延伸穿过第三层和第二层以到达第一层。栅极绝缘膜覆盖栅极沟槽的侧壁。栅极电极嵌入栅极沟槽中，栅极绝缘膜插入其间。

4. 发明申请

US20130075758A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20130075758A1
公开(公告)日：2013-03-28
申请号：US13613801
申请日：2012-09-13
申请人： Takeyoshi MASUDA , Keiji WADA , Toru HIYOSHI
发明人： Takeyoshi MASUDA , Keiji WADA , Toru HIYOSHI
IPC分类号： H01L29/78 , H01L21/265 , H01L29/24
CPC分类号： H01L21/265 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection.
摘要翻译： MOSFET包括具有形成在主表面中的沟槽，栅极氧化膜，栅极电极和源极互连的半导体衬底。半导体衬底包括n型漂移层和p型体层。沟槽形成为穿透身体层并到达漂移层。所述沟槽包括外围沟槽，所述外周沟槽布置为在二维地观察时围绕有源区域。在从外周沟槽观察时在与有源区域相反的主表面上形成有体层露出的电位固定区域。当二维观察时，源极互连布置成位于有源区上。电位固定区域电连接到源互连。

5. 发明申请

US20130065384A1 METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US20130065384A1
公开(公告)日：2013-03-14
申请号：US13613785
申请日：2012-09-13
申请人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
发明人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/02529 , H01L21/0262 , H01L21/0475 , H01L21/3065 , H01L21/3081 , H01L29/045 , H01L29/0623 , H01L29/1608 , H01L29/4236 , H01L29/4238 , H01L29/66068 , H01L29/7397
摘要： A mask layer is formed on a silicon carbide layer by a deposition method. The mask layer is patterned. A gate trench having a side wall is formed by removing a portion of the silicon carbide layer by etching using the patterned mask layer as a mask. A gate insulating film is formed on the side wall of the gate trench. A gate electrode is formed on the gate insulating film. The silicon carbide layer has one of hexagonal and cubic crystal types, and the side wall of the gate trench substantially includes one of a{0-33-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.
摘要翻译：通过沉积方法在碳化硅层上形成掩模层。掩模层被图案化。通过使用图案化掩模层作为掩模的蚀刻去除碳化硅层的一部分来形成具有侧壁的栅极沟槽。栅极绝缘膜形成在栅极沟槽的侧壁上。在栅极绝缘膜上形成栅电极。碳化硅层具有六方晶体和立方晶体中的一种，栅极沟槽的侧壁基本上包括{0-33-8}面和{01-1-4}面之一，在硅碳化物层为六方晶系，并且在碳化硅层为立方晶型的情况下，基本上包含{100}面。

6. 发明申请

US20120326166A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120326166A1
公开(公告)日：2012-12-27
申请号：US13529602
申请日：2012-06-21
申请人： Takeyoshi Masuda , Shin Harada , Keiji Wada , Toru Hiyoshi
发明人： Takeyoshi Masuda , Shin Harada , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/24 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/049 , H01L21/3065 , H01L29/045 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7397 , H01L29/7813
摘要： A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.
摘要翻译：衬底具有由具有多晶型4H的六方晶单晶结构的半导体制成的表面。基板的表面通过交替地提供具有（0-33-8）的平面取向的第一平面和连接到第一平面并具有不同于第一平面的平面取向的平面取向的第二平面来构造。栅极绝缘膜设置在基板的表面上。在栅极绝缘膜上设置栅电极。

7. 发明申请

US20120228640A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120228640A1
公开(公告)日：2012-09-13
申请号：US13512456
申请日：2011-07-14
申请人： Takeyoshi Masuda , Shin Harada , Misako Honaga , Keiji Wada , Toru Hiyoshi
发明人： Takeyoshi Masuda , Shin Harada , Misako Honaga , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/24 , H01L21/04
CPC分类号： H01L29/66068 , H01L21/046 , H01L21/0475 , H01L21/3065 , H01L29/045 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/1608 , H01L29/4236 , H01L29/6606 , H01L29/7397 , H01L29/7813 , H01L29/8613 , H01L29/868
摘要： There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region.
摘要翻译：提供了具有稳定特性的高质量半导体器件和制造这种半导体器件的方法。半导体器件包括：具有主表面的衬底; 以及形成在所述基板的主表面上并且包括相对于所述主表面倾斜的侧表面的碳化硅层。侧表面基本上包括{03-3-8}平面。侧面包括通道区域。

8. 发明申请

US20120208368A1 METHOD AND APPARATUS FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造碳化硅半导体器件的方法和装置
公开(公告)号：US20120208368A1
公开(公告)日：2012-08-16
申请号：US13502976
申请日：2011-02-25
申请人： Takeyoshi Masuda , Keiji Wada , Satomi Itoh , Toru Hiyoshi
发明人： Takeyoshi Masuda , Keiji Wada , Satomi Itoh , Toru Hiyoshi
IPC分类号： H01L21/31 , H01L21/308
CPC分类号： H01L29/7802 , H01L21/02057 , H01L21/02236 , H01L21/02301 , H01L21/0445 , H01L21/049 , H01L29/1608 , H01L29/66053 , H01L29/66068
摘要： A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.
摘要翻译：一种制造SiC半导体器件的方法包括以下步骤：在SiC半导体的第一表面上形成第一氧化物膜，去除第一氧化物膜，以及在第二表面上形成构成SiC半导体器件的第二氧化膜，去除SiC半导体中第一氧化膜的结果。在除去第一氧化物膜的步骤和形成第二氧化物膜的步骤之间，将SiC半导体布置在从环境气氛切断的气氛中。

9. 发明申请

US20110309376A1 METHOD OF CLEANING SILICON CARBIDE SEMICONDUCTOR, SILICON CARBIDE SEMICONDUCTOR, AND SILICON CARBIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：清洁碳化硅半导体，碳化硅半导体和碳化硅半导体器件的方法
公开(公告)号：US20110309376A1
公开(公告)日：2011-12-22
申请号：US13102660
申请日：2011-05-06
申请人： Toru HIYOSHI , Keiji WADA , Takeyoshi MASUDA , Hiromu SHIOMI , Satomi ITOH , Tomihito MIYAZAKI
发明人： Toru HIYOSHI , Keiji WADA , Takeyoshi MASUDA , Hiromu SHIOMI , Satomi ITOH , Tomihito MIYAZAKI
IPC分类号： H01L29/161 , H01L21/306
CPC分类号： H01L29/7802 , H01L21/02043 , H01L21/02052 , H01L21/02054 , H01L21/02236 , H01L21/02378 , H01L21/02529 , H01L21/02658 , H01L21/044 , H01L21/049 , H01L29/1608 , H01L29/66068
摘要： A method of cleaning an SiC semiconductor capable of exhibiting an effect of cleaning an SiC semiconductor is provided. An SiC semiconductor and an SiC semiconductor device capable of achieving improved characteristics are provided. The method of cleaning an SiC semiconductor includes the steps of forming an oxide film on a surface of an SiC semiconductor (step S2) and removing the oxide film (step S3). In the forming step (step S2), the oxide film is formed in a dry atmosphere at a temperature not lower than 700° C. that contains O element. The SiC semiconductor is an SiC semiconductor having a surface and the surface has metal surface density not higher than 1×1012 cm−2. The SiC semiconductor device includes an SiC semiconductor and an oxide film formed on a surface of the SiC semiconductor.
摘要翻译：提供了一种能够显示清洁SiC半导体效果的SiC半导体的清洗方法。提供能够实现改进的特性的SiC半导体和SiC半导体器件。清洗SiC半导体的方法包括以下步骤：在SiC半导体的表面上形成氧化膜（步骤S2）并除去氧化膜（步骤S3）。在成形步骤（步骤S2）中，氧化膜在含有O元素的不低于700℃的干燥气氛中形成。 SiC半导体是具有表面且表面的金属表面密度不高于1×1012cm-2的SiC半导体。 SiC半导体器件包括形成在SiC半导体的表面上的SiC半导体和氧化物膜。

10. 发明授权

US6084089A Cold-inducible promoter sequences 失效
标题翻译：冷诱导启动子序列
公开(公告)号：US6084089A
公开(公告)日：2000-07-04
申请号：US894731
申请日：1997-10-27
申请人： Toshiki Mine , Akio Ohyama , Toru Hiyoshi , Keisuke Kasaoka
发明人： Toshiki Mine , Akio Ohyama , Toru Hiyoshi , Keisuke Kasaoka
IPC分类号： C07K14/415 , C12N15/11 , C12N15/29 , C12N15/82 , C12Q1/68 , C07H21/04 , C07H21/02
CPC分类号： C07K14/415 , C12N15/8226 , C12N15/8237
摘要： This invention discloses a novel cold-inducible promoter which induces gene expression at low temperatures in potato tubers but which is scarcely induced in organs other than tuber or at normal temperature, which induces gene expression for a long time not less than five months. The promoters of this invention are the DNA sequence having a nucleotide sequence from first to 3546th nucleotide in the nucleotide sequence shown in SEQ ID NO: 1, or a part thereof having a cold-inducible promoter activity, or a DNA sequence having the same nucleotide sequence as said DNA sequences except that one or more nucleotides are deleted or substituted, or one or more nucleotides are inserted or added, which DNA sequence has a cold-inducible promoter activity and the DNA sequence having a nucleotide sequence from first to 4120th nucleotide in the nucleotide sequence shown in SEQ ID NO: 2, or a part thereof having a cold-inducible promoter activity, or a DNA sequence having the same nucleotide sequence as the said DNA sequences except that one or more nucleotides are deleted or substituted, or one or more nucleotides are inserted or added, which DNA sequence has a cold-inducible promoter activity.
摘要翻译： PCT No.PCT / JP96 / 03822 Sec。 371日期1997年10月27日第 102（e）日期1997年10月27日PCT 1996年12月26日PCT公布。第WO97 / 24449号公报日本1997年7月10日本发明公开了一种在马铃薯块茎中诱导低温基因表达的新型冷诱导型启动子，但在块茎以外的器官或常温下几乎不诱导基因表达，其诱导基因表达长时间不小于五个月。本发明的启动子是具有SEQ ID NO：1所示核苷酸序列的第一至第3546位核苷酸序列的DNA序列或其具有冷诱导型启动子活性的部分的DNA序列，或具有相同核苷酸的DNA序列序列作为所述DNA序列，除了一个或多个核苷酸被缺失或取代，或插入或添加一个或多个核苷酸，哪个DNA序列具有冷诱导启动子活性，并且DNA序列具有从第一至第4120位核苷酸的核苷酸序列 SEQ ID NO：2所示的核苷酸序列或其具有冷诱导型启动子活性的部分，或具有与所述DNA序列相同的核苷酸序列的DNA序列，除了一个或多个核苷酸被缺失或取代，或一个或更多个核苷酸插入或添加，哪个DNA序列具有冷诱导型启动子活性。

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