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1. 发明授权

US08513037B2 Method of integrating slotted waveguide into CMOS process 有权
标题翻译：将开槽波导集成到CMOS工艺中的方法
公开(公告)号：US08513037B2
公开(公告)日：2013-08-20
申请号：US13580872
申请日：2011-12-02
申请人： Andrew T S Pomerene , Craig M. Hill , Timothy J. Conway , Stewart L. Ocheltree
发明人： Andrew T S Pomerene , Craig M. Hill , Timothy J. Conway , Stewart L. Ocheltree
IPC分类号： H01P1/15
CPC分类号： H01L27/13 , H01L21/84 , H01L27/1463 , H01L27/14683
摘要： A method for integrating a slotted waveguide into a CMOS process is disclosed. A slot can be patterned on a SOI wafer by etching a first pad hard mask deposited over the wafer. The slot is then filled with a nitride plug material by depositing a second pad hard mask over the first pad hard mask. A waveguide in association with one or more electronic and photonic devices can also be patterned on the SOI wafer. The trenches can be filled with an isolation material and then polished. Thereafter, the first and second pad hard masks can be stripped from the wafer. The slot can once again be filled with the nitride plug material and patterned. After forming one or more electronic and photonic devices on the wafer using a standard CMOS process, a via can be opened down to the nitride plug and the nitride plug can then be removed.
摘要翻译：公开了一种将时隙波导集成到CMOS工艺中的方法。通过蚀刻沉积在晶片上的第一焊盘硬掩模，可以在SOI晶片上图案化槽。然后通过在第一焊盘硬掩模上沉积第二焊盘硬掩模，然后用氮化物塞材料填充槽。与一个或多个电子和光子器件相关联的波导也可以在SOI晶片上图案化。沟槽可以用隔离材料填充，然后抛光。此后，可以从晶片剥离第一和第二焊盘硬掩模。该槽可再次填充氮化物塞材料并图案化。在使用标准CMOS工艺在晶片上形成一个或多个电子和光子器件之后，可以将通孔向下打开到氮化物塞，然后可以去除氮化物塞。

2. 发明申请

US20120252158A1 Method for Manufacturing Lateral Germanium Detectors 失效
标题翻译：制造侧向锗探测器的方法
公开(公告)号：US20120252158A1
公开(公告)日：2012-10-04
申请号：US12521853
申请日：2008-10-27
申请人： Daniel N. Carothers , Craig M. Hill , Andrew T. S. Pomerene , Vu A. Vu , Robert Kamocsai , Timothy J. Conway
发明人： Daniel N. Carothers , Craig M. Hill , Andrew T. S. Pomerene , Vu A. Vu , Robert Kamocsai , Timothy J. Conway
IPC分类号： H01L31/18
CPC分类号： H01L27/1467
摘要： An improved method for manufacturing a lateral germanium detector is disclosed. A detector window is opened through an oxide layer to expose a doped single crystalline silicon layer situated on a substrate. Next, a single crystal germanium layer is grown within the detector window, and an amorphous germanium layer is grown on the oxide layer. The amorphous germanium layer is then polished to leave only a small portion around the single crystal germanium layer. A dielectric layer is deposited on the amorphous germanium layer and the single crystal germanium layer. Using resist masks and ion implants, multiple doped regions are formed on the single crystal germanium layer. After opening several oxide windows on the dielectric layer, a refractory metal layer is deposited on the doped regions to form multiple germanide layers.
摘要翻译：公开了用于制造侧向锗检测器的改进方法。检测器窗口通过氧化物层打开以暴露位于衬底上的掺杂单晶硅层。接下来，在检测器窗口内生长单晶锗层，并且在氧化物层上生长非晶锗层。然后抛光无定形锗层以在单晶锗层周围仅留下一小部分。介电层沉积在非晶锗层和单晶锗层上。使用抗蚀剂掩模和离子注入，在单晶锗层上形成多个掺杂区。在介电层上打开几个氧化物窗后，在掺杂区域上沉积难熔金属层以形成多个锗化物层。

3. 发明申请

US20100140708A1 Multi-Thickness Semiconductor with Fully Depleted Devices and Photonic Integration 有权
标题翻译：具有完全耗尽器件和光子整合的多厚度半导体
公开(公告)号：US20100140708A1
公开(公告)日：2010-06-10
申请号：US12328853
申请日：2008-12-05
申请人： Craig M. Hill , Andrew T. Pomerene , Daniel N. Carothers , Timothy J. Conway , Vu A. Vu
发明人： Craig M. Hill , Andrew T. Pomerene , Daniel N. Carothers , Timothy J. Conway , Vu A. Vu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , G02B6/136 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.
摘要翻译：公开了促进包括不同厚度的结构和器件的半导体的制造的技术。一个实施例提供了一种用于半导体器件制造的方法，其包括使要形成器件的半导体晶片的区域变薄从而限定晶片的薄区域和厚区域。该方法继续在厚区域上形成一个或多个光子器件和/或部分耗尽的电子器件，并且在薄区域上形成一个或多个完全耗尽的电子器件。另一个实施例提供一种半导体器件，其包括限定薄区域和厚区域的半导体晶片。该器件还包括形成在厚区域上的一个或多个光子器件和/或部分耗尽的电子器件，以及形成在薄区域上的一个或多个完全耗尽的电子器件。可以在薄区域和厚区域之间形成隔离区域。

4. 发明授权

US5067099A Methods and apparatus for monitoring system performance 失效
标题翻译：监测系统性能的方法和装置
公开(公告)号：US5067099A
公开(公告)日：1991-11-19
申请号：US335464
申请日：1989-04-10
申请人： Patricia M. McCown , Timothy J. Conway , Karl M. Jessen
发明人： Patricia M. McCown , Timothy J. Conway , Karl M. Jessen
IPC分类号： G06F11/22 , G06F11/25 , G06F11/34
CPC分类号： G06F11/2257 , G06F11/34
摘要： Method and apparatus for performing system monitoring and diagnostics is disclosed. In performing system monitoring, data is acquired from the system under test and compared to an event model. The event model comprises a database having event records which pre-define events which can occur. Each event record includes a state vector dependency which lists the events which must occur prior to the pre-defined event occurring and one or more critical parameters defining the data which must occur during the system's performance for the event to have occurred. Event recognition is performed by comparing each event record to acquired operational data and to events already recognized. Associated with each event record in the database is an intelligent data acquisition action which defines an action to be taken as a result of the event record being recognized. These actions can modify the performance of the system being monitored or the acquisition of data. Additionally, the results of the event recognition step can be further analyzed in a computer.
摘要翻译：公开了用于执行系统监视和诊断的方法和装置。在执行系统监视时，从被测系统中获取数据，并与事件模型进行比较。事件模型包括具有预定义可能发生的事件的事件记录的数据库。每个事件记录包括一个状态向量依赖关系，其列出必须在预定义事件发生之前发生的事件以及一个或多个关键参数，该关键参数定义在系统执行事件期间必须发生的数据。通过将每个事件记录与获取的操作数据和已经识别的事件进行比较来执行事件识别。与数据库中的每个事件记录相关联的是智能数据采集动作，其定义由于识别事件记录而被采取的动作。这些操作可以修改正在监视的系统或数据采集的性能。此外，可以在计算机中进一步分析事件识别步骤的结果。

5. 发明申请

US20120322177A1 METHOD OF INTEGRATING SLOTTED WAVEGUIDE INTO CMOS PROCESS 有权
标题翻译：将插入式波导集成到CMOS工艺中的方法
公开(公告)号：US20120322177A1
公开(公告)日：2012-12-20
申请号：US13580872
申请日：2011-12-02
申请人： Andrew TS Pomerene , Craig M. Hill , Timothy J. Conway , Stewart L. Ocheltree
发明人： Andrew TS Pomerene , Craig M. Hill , Timothy J. Conway , Stewart L. Ocheltree
IPC分类号： H01L33/00 , H01L31/0216
CPC分类号： H01L27/13 , H01L21/84 , H01L27/1463 , H01L27/14683
摘要： A method for integrating a slotted waveguide into a CMOS process is disclosed. A slot can be patterned on a SOI wafer by etching a first pad hard mask deposited over the wafer. The slot is then filled with a plug material by depositing a second pad hard mask over the first pad hard mask. A waveguide in association with one or more electronic and photonic devices can also be patterned on the SOI wafer. The trenches can be filled with an isolation material and then polished. Thereafter, the first and second pad hard masks can be stripped from the wafer. The slot can once again be filled with the plug material and patterned. After forming one or more electronic and photonic devices on the wafer using the standard CMOS process, a via can be opened up down to the nitride plug and the nitride plug can then be removed.
摘要翻译：公开了一种将时隙波导集成到CMOS工艺中的方法。通过蚀刻沉积在晶片上的第一焊盘硬掩模，可以在SOI晶片上图案化槽。然后通过在第一焊盘硬掩模上沉积第二焊盘硬掩模来将插槽用插塞材料填充。与一个或多个电子和光子器件相关联的波导也可以在SOI晶片上图案化。沟槽可以用隔离材料填充，然后抛光。此后，可以从晶片剥离第一和第二焊盘硬掩模。该槽可再次填充塞子材料并图案化。在使用标准CMOS工艺在晶片上形成一个或多个电子和光子器件之后，可以将通孔向下打开到氮化物塞，然后可以去除氮化物塞。

6. 发明授权

US07847353B2 Multi-thickness semiconductor with fully depleted devices and photonic integration 有权
标题翻译：具有完全耗尽器件和光子整合的多厚度半导体
公开(公告)号：US07847353B2
公开(公告)日：2010-12-07
申请号：US12328853
申请日：2008-12-05
申请人： Craig M. Hill , Andrew T. Pomerene , Daniel N. Carothers , Timothy J. Conway , Vu A. Vu
发明人： Craig M. Hill , Andrew T. Pomerene , Daniel N. Carothers , Timothy J. Conway , Vu A. Vu
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , G02B6/136 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.
摘要翻译：公开了促进包括不同厚度的结构和器件的半导体的制造的技术。一个实施例提供了一种用于半导体器件制造的方法，其包括使要形成器件的半导体晶片的区域变薄从而限定晶片的薄区域和厚区域。该方法继续在厚区域上形成一个或多个光子器件和/或部分耗尽的电子器件，并且在薄区域上形成一个或多个完全耗尽的电子器件。另一个实施例提供一种半导体器件，其包括限定薄区域和厚区域的半导体晶片。该器件还包括形成在厚区域上的一个或多个光子器件和/或部分耗尽的电子器件，以及形成在薄区域上的一个或多个完全耗尽的电子器件。可以在薄区域和厚区域之间形成隔离区域。

7. 发明申请

US20100092682A1 Method for Fabricating a Heater Capable of Adjusting Refractive Index of an Optical Waveguide 审中-公开
$Method for Fabricating a Heater Capable of Adjusting Refractive Index of an Optical Waveguide$
标题翻译：制造能够调整光波导折射率的加热器的方法
公开(公告)号：US20100092682A1
公开(公告)日：2010-04-15
申请号：US12521855
申请日：2008-08-29
申请人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Thomas J. McIntyre , Timothy J. Conway , Jonathan N. Ishii
发明人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Thomas J. McIntyre , Timothy J. Conway , Jonathan N. Ishii
IPC分类号： B05D3/02
CPC分类号： G02B6/10 , G02B6/12033 , G02F1/011 , G02F1/0147
摘要： A method for fabricating a thermal optical heating element capable of adjusting refractive index of an optical waveguide is disclosed. A silicon block is initially formed on a cladding layer on a silicon substrate. The silicon block is located in close proximity to an optical waveguide. A cobalt layer is deposited on the silicon block. The silicon block is then annealed to cause the cobalt layer to react with the silicon block to form a cobalt silicide layer. The silicon block is again annealed to cause the cobalt silicide layer to transform into a cobalt di-silicide layer.
摘要翻译：公开了一种制造能够调节光波导的折射率的热光学加热元件的方法。最初在硅衬底上的包覆层上形成硅块。硅块位于靠近光波导的位置。钴层沉积在硅块上。然后将硅块退火以使钴层与硅块反应形成硅化钴层。再次退火硅块以使硅化钴层转变成二硅化钴层。

8. 发明申请

US20090111200A1 Method for Fabricating Electronic and Photonic Devices on a Semiconductor Substrate 有权
标题翻译：在半导体基板上制造电子和光子器件的方法
公开(公告)号：US20090111200A1
公开(公告)日：2009-04-30
申请号：US12201943
申请日：2008-08-29
申请人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Timothy J. Conway , Rick L. Thompson , Vu A. Vu , Robert Kamocsai , Joe Giunta , Jonathan N. Ishii
发明人： Daniel N. Carothers , Craig M. Hill , Andrew T.S. Pomerene , Timothy J. Conway , Rick L. Thompson , Vu A. Vu , Robert Kamocsai , Joe Giunta , Jonathan N. Ishii
IPC分类号： H01L21/02
CPC分类号： H01L27/0617
摘要： A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate.
摘要翻译：公开了一种在衬底上制造光子和电子器件的方法。最初对多个板坯进行图案化并在衬底层上进行蚀刻。在第一板上制造电子器件，并且在第二板上制造光子器件，使得电子器件和光子器件形成在基片的同一层上。

9. 发明授权

US5099436A Methods and apparatus for performing system fault diagnosis 失效
标题翻译：执行系统故障诊断的方法和装置
公开(公告)号：US5099436A
公开(公告)日：1992-03-24
申请号：US266722
申请日：1988-11-03
申请人： Patricia M. McCown , Timothy J. Conway
发明人： Patricia M. McCown , Timothy J. Conway
IPC分类号： G06F11/25 , G06F11/34
CPC分类号： G06F11/2257 , G06F11/34 , Y10S706/911
摘要： A diagnostic tool based on a hybrid knowledge representation of a system under test is disclosed. Data collected from the system during its operation is compared to an event based representation of the system which comprises a plurality of predefined events. An event is recognized when the collected data matches the event's critical parameter. The recognized event is analyzed and an associated set of ambiguity group effects, which specify components to be re-ranked in an ambiguity group according to an associated ranking effect. Additonally, a symptom-fault model and a failure model can be analyzed to determine symptom-fault relationships and failure modes which are applicable to the system operation. Each applicable symptom-fault relationship and failure mode is also associated with a set of ambiguity group effects which rerank the ambiguity group. A structural model is analyzed starting with the components in the ambiguity group having the greatest probability of failure. As a result of the analysis, maintenance options specifying tests to be performed on the system are output.
摘要翻译：公开了一种基于被测系统的混合知识表示的诊断工具。在系统运行期间收集的数据与包括多个预定义事件的系统的基于事件的表示进行比较。当收集的数据与事件的关键参数匹配时，会识别事件。分析识别的事件和相关的一组模糊组效应，其根据相关的排序效果来指定要在歧义组中重新排列的组件。此外，可以分析症状 - 故障模型和故障模型，以确定适用于系统操作的症状 - 故障关系和故障模式。每个适用的症状 - 故障关系和故障模式也与重新设定歧义组的一组模糊组效应相关联。从具有最大故障概率的模糊组中的组件开始分析结构模型。作为分析的结果，输出指定要在系统上执行的测试的维护选项。

10. 发明授权

US08192638B2 Method for manufacturing multiple layers of waveguides 有权
标题翻译：制造多层波导的方法
公开(公告)号：US08192638B2
公开(公告)日：2012-06-05
申请号：US12517692
申请日：2008-08-29
申请人： Andrew T. S. Pomerene , Timothy J. Conway , Craig M. Hill , Mark Jaso
发明人： Andrew T. S. Pomerene , Timothy J. Conway , Craig M. Hill , Mark Jaso
IPC分类号： B29D11/00 , G02B6/10 , G02F1/00
CPC分类号： G02B6/12002 , B82Y20/00 , G02B6/1223 , G02B6/132 , G02B6/136
摘要： A method for manufacturing multiple layers of waveguides is disclosed. Initially, a first cladding layer is deposited on a substrate, a first inner cladding layer is then deposited on the first cladding layer, and a first waveguide material is deposited on the first inner cladding layer. The first inner cladding layer and the first waveguide material are then selectively etched to form a first waveguide layer. Next, a second inner cladding layer followed by a second cladding layer are deposited on the first waveguide layer. The second inner cladding layer and the second cladding layer are removed by using a chemical-mechanical polishing process selective to the first waveguide material. A third inner cladding layer followed by a second waveguide material are deposited on the first waveguide material. The third inner cladding layer and the second waveguide material are then selectively etched to form a second waveguide layer. Finally, a fourth inner cladding layer followed by a third cladding layer are deposited on the second waveguide layer.
摘要翻译：公开了制造多层波导的方法。首先，在基板上沉积第一包层，然后在第一包层上沉积第一内包层，在第一内包层上沉积第一波导材料。然后选择性地蚀刻第一内包层和第一波导材料以形成第一波导层。接下来，在第一波导层上沉积第二内包层和第二覆层。通过使用对第一波导材料选择性的化学机械抛光工艺来除去第二内包层和第二包覆层。在第一波导材料上沉积第三内包层和第二波导材料。然后选择性地蚀刻第三内包层和第二波导材料以形成第二波导层。最后，在第二波导层上沉积第四内包层和第三覆层。

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