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2. 发明授权

US06590198B1 Video bus for high speed multi-resolution imagers 有权
标题翻译：用于高速多分辨率成像器的视频总线
公开(公告)号：US06590198B1
公开(公告)日：2003-07-08
申请号：US09490374
申请日：2000-01-24
申请人： Jeffrey Zarnowski , Matthew Pace , Thomas Vogelsong , Michael Joyner
发明人： Jeffrey Zarnowski , Matthew Pace , Thomas Vogelsong , Michael Joyner
IPC分类号： H01J4014
CPC分类号： H04N5/3658 , H04N5/347 , H04N5/365 , H04N5/3742 , H04N5/37457 , H04N5/378
摘要： An analog video bus architecture that utilizes the column parallel nature of CMOS imagers and more specifically Active Column Sensors, that eliminates the need for multi-port imagers, by increasing the useable bandwidth of single port imagers. An adaptation of this invention allows for either binning or interpolation of pixel information for increased or decreased resolution along the columns and more specifically for ACS imagers binning or interpolation along the rows. In this bus, the single video bus is replaced by multiple video buses and instead of selecting only one column for reading multiple columns are also pre-selected in-order to pre-charge the video bus. The video buses are then de-multiplexed back on to one port at the desired element rate. This architecture utilizes the column oriented video bus of CMOS imagers. It divides the large video bus capacitance by the number of video buses used. In addition, it allows multiple pixel time constants to precharge the video bus. The best commercially available imager designs now claim 40 MHz per analog port and suffer from reduced signal to noise ratios. To overcome this fundamental bandwidth limitation, imager designs in the past have had to increase the number of video ports per imager to achieve high frame rates. Multiple ports per imager breaks the focal plane into segments that are typically reassembled via post processing in a host computer. The other problem with multiple ports is each segment of the imager will have its own offsets and resultant Fixed Pattern Noise (FPN). PVS-Bus™ eliminates the objectionable segmentation and simplifies high-speed system design. Also, by utilizing the column parallel nature of CMOS video buses a method and improved method of using the PVS-Bus of binning and interpolation is described which results in increased frame rate, and for decreased or increased resolution.
摘要翻译：模拟视频总线架构通过增加单端口成像器的可用带宽，利用CMOS成像器的列并行特性，更具体地说是活动列传感器，消除了对多端口成像器的需要。本发明的适应性允许对沿着列的分辨率增加或降低的像素信息进行合并或插值，更具体地说，用于沿着行的ACS成像器合并或内插。在该总线中，单视频总线被多个视频总线替代，而不是仅选择一列用于读取多个列，也是预先选择的，以便为视频总线预充电。然后视频总线以所需的元件速率被反复复用到一个端口。该架构利用了CMOS成像器的面向列的视频总线。它将大视频总线电容除以所使用的视频总线数量。另外，它允许多个像素时间常数来预充电视频总线。市面上最好的成像器设计现在要求每个模拟端口40 MHz，信噪比降低。为了克服这种基本的带宽限制，过去的成像器设计不得不增加每个成像器的视频端口的数量以实现高帧速率。每个成像仪的多个端口将焦平面分解成通常通过主机中的后处理重新组合的段。多个端口的另一个问题是成像器的每个段将具有其自己的偏移量和结果固定模式噪声（FPN）。 PVS-Bus（TM）消除了令人反感的分割，简化了高速系统设计。此外，通过利用CMOS视频总线的列并行性，描述了使用分组和内插的PVS-Bus的方法和改进的方法，其导致帧速率增加以及分辨率降低或增加。

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