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1. 发明授权

US6133759A Decoupled reset dynamic logic circuit 失效
标题翻译：去耦合复位动态逻辑电路
公开(公告)号：US6133759A
公开(公告)日：2000-10-17
申请号：US97794
申请日：1998-06-16
申请人： John Andrew Beck , Robert Paul Masleid , Thomas Robert Toms
发明人： John Andrew Beck , Robert Paul Masleid , Thomas Robert Toms
IPC分类号： H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A dynamic logic circuit is implemented which decouples the reset of the output from the reset of the evaluation node. An N-tree logic circuit generates a logical output signal in response to a first set of input signals. The output signal is coupled to a gate of a first n-type field effect transistor (NFET) of a parallel coupled pair of NFET devices. The parallel drains are coupled to an output of the dynamic logic circuit and the parallel sources are coupled to ground. The gate of the second NFET device of the pair is coupled to the junction of a source and drain, respectively, of a series connected p-type field effect transistor (PFET) device, and a third NFET device. The third NFET device has a source coupled to ground, and the PFET device has a drain coupled to a voltage supply. Gates of the PFET device and the third NFET device are connected together and receive a logic signal whereby the output of the dynamic logic circuit may be reset.
摘要翻译：实现了动态逻辑电路，其将输出的复位与评估节点的复位分离。 N树逻辑电路响应于第一组输入信号产生逻辑输出信号。输出信号耦合到并联耦合的一对NFET器件的第一n型场效应晶体管（NFET）的栅极。并联漏极耦合到动态逻辑电路的输出，并联源耦合到地。该对的第二NFET器件的栅极分别耦合到串联连接的p型场效应晶体管（PFET）器件和第三NFET器件的源极和漏极的结。第三NFET器件具有耦合到地的源极，并且PFET器件具有耦合到电压源的漏极。 PFET器件和第三NFET器件的栅极连接在一起并接收逻辑信号，由此可以复位动态逻辑电路的输出。

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