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1. 发明授权

US08732386B2 Sharing data fabric for coherent-distributed caching of multi-node shared-distributed flash memory 有权
标题翻译：共享数据结构，用于多节点共享分布式闪存的相干分布式缓存
公开(公告)号：US08732386B2
公开(公告)日：2014-05-20
申请号：US12197899
申请日：2008-08-25
申请人： Brian Walter O'Krafka , Michael John Koster , Darpan Dinker , Earl T. Cohen , Thomas M. McWilliams
发明人： Brian Walter O'Krafka , Michael John Koster , Darpan Dinker , Earl T. Cohen , Thomas M. McWilliams
IPC分类号： G06F12/00
CPC分类号： G06F12/0284 , G06F12/0806 , G06F12/0866 , G06F2212/1044 , G06F2212/2022 , G06F2212/2542 , Y02D10/13
摘要： A Sharing Data Fabric (SDF) causes flash memory attached to multiple compute nodes to appear to be a single large memory space that is global yet shared by many applications running on the many compute nodes. Flash objects stored in flash memory of a home node are copied to an object cache in DRAM at an action node by SDF threads executing on the nodes. The home node has a flash object map locating flash objects in the home node's flash memory, and a global cache directory that locates copies of the object in other sharing nodes. Application programs use an applications-programming interface (API) into the SDF to transparently get and put objects without regard to the object's location on any of the many compute nodes. SDF threads and tables control coherency of objects in flash and DRAM.
摘要翻译：共享数据结构（SDF）使得连接到多个计算节点的闪存看起来是由许多计算节点上运行的许多应用程序全局而共享的单个大内存空间。存储在家庭节点的闪存中的闪存对象通过在节点上执行的SDF线程在动作节点处复制到DRAM中的对象缓存。家庭节点具有在家庭节点的闪存中定位闪存对象的闪存对象映射，以及将对象的副本定位在其他共享节点中的全局高速缓存目录。应用程序使用应用程序编程接口（API）到SDF中透明地获取和放置对象，而不考虑对象在许多计算节点上的位置。 SDF线程和表控制闪存和DRAM中对象的一致性。

2. 发明授权

US07076416B2 Method and apparatus for evaluating logic states of design nodes for cycle-based simulation 有权
标题翻译：用于评估基于循环的仿真的设计节点的逻辑状态的方法和装置
公开(公告)号：US07076416B2
公开(公告)日：2006-07-11
申请号：US10105754
申请日：2002-03-25
申请人： Liang T. Chen , William kwei-cheung Lam , Thomas M. McWilliams
发明人： Liang T. Chen , William kwei-cheung Lam , Thomas M. McWilliams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.
摘要翻译：用于评估设计节点的逻辑状态的方法包括编译逻辑设计以生成注释符号表和级别化设计，从级别化设计获得逻辑评估成本，使用逻辑评估成本来定位策略节点，标记战略节点，并使用注释符号表，策略节点和级别化设计来计算设计节点的逻辑状态。

3. 发明授权

US08667212B2 System including a fine-grained memory and a less-fine-grained memory 有权
标题翻译：系统包括细粒度的内存和较细粒度的内存
公开(公告)号：US08667212B2
公开(公告)日：2014-03-04
申请号：US13584755
申请日：2012-08-13
申请人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
发明人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
IPC分类号： G06F12/00
CPC分类号： G06F12/0284 , G06F12/0802 , G06F12/0806 , G06F2212/1044 , G06F2212/2022 , G06F2212/2542 , G06F2212/401 , Y02D10/13
摘要： A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
摘要翻译：数据处理系统包括一个或多个节点，每个节点包括存储器子系统。该子系统包括细粒度的存储器和不太细粒度的（例如基于页面的）存储器。细粒度的内存可选地用作基于页面的存储器的缓存和/或写入缓冲器。在系统上执行的软件使用节点地址空间，其能够访问所有节点的基于页面的存储器。每个节点可选地为该空间的至少一部分提供ACID存储器属性。在空间的至少一部分中，存储器元素被映射到基于页的存储器中的位置。在各种实施例中，一些元素被压缩，压缩的元素被打包成页面，页面被写入基于页面的存储器中的可用位置，并且映射维持一些元素和位置之间的关联。

4. 发明授权

US07975109B2 System including a fine-grained memory and a less-fine-grained memory 有权
标题翻译：系统包括细粒度的内存和较细粒度的内存
公开(公告)号：US07975109B2
公开(公告)日：2011-07-05
申请号：US12130661
申请日：2008-05-30
申请人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
发明人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
IPC分类号： G06F12/00
CPC分类号： G06F12/0284 , G06F12/0802 , G06F12/0806 , G06F2212/1044 , G06F2212/2022 , G06F2212/2542 , G06F2212/401 , Y02D10/13
摘要： A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
摘要翻译：数据处理系统包括一个或多个节点，每个节点包括存储器子系统。子系统包括细粒度的存储器和较细粒度的（例如基于页面的）存储器。细粒度的内存可选地用作基于页面的存储器的缓存和/或写入缓冲器。在系统上执行的软件使用节点地址空间，其能够访问所有节点的基于页面的存储器。每个节点可选地为该空间的至少一部分提供ACID存储器属性。在空间的至少一部分中，存储器元素被映射到基于页的存储器中的位置。在各种实施例中，一些元素被压缩，压缩的元素被打包成页面，页面被写入基于页面的存储器中的可用位置，并且地图保持一些元素和位置之间的关联。

5. 发明授权

US07036114B2 Method and apparatus for cycle-based computation 有权
公开(公告)号：US07036114B2
公开(公告)日：2006-04-25
申请号：US10113005
申请日：2002-03-29
申请人： Thomas M. McWilliams , Jeffrey B. Rubin , Derek E. Pappas , Oyekunle A. Olukotun , Jeffrey M. Broughton , David R. Emberson , William kwei-cheung Lam , Liang T. Chen , Ihao Chen , Earl T. Cohen , Michael W. Parkin
发明人： Thomas M. McWilliams , Jeffrey B. Rubin , Derek E. Pappas , Oyekunle A. Olukotun , Jeffrey M. Broughton , David R. Emberson , William kwei-cheung Lam , Liang T. Chen , Ihao Chen , Earl T. Cohen , Michael W. Parkin
IPC分类号： G06F9/45
CPC分类号： G06F17/5022 , G06F2217/68
摘要： A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

6. 发明授权

US06772299B2 Method and apparatus for caching with variable size locking regions 有权
标题翻译：用可变大小锁定区域缓存的方法和装置
公开(公告)号：US06772299B2
公开(公告)日：2004-08-03
申请号：US10141249
申请日：2002-05-08
申请人： Thomas M. McWilliams , Earl T. Cohen
发明人： Thomas M. McWilliams , Earl T. Cohen
IPC分类号： G06F1200
CPC分类号： G06F12/126
摘要： A method of managing data in a cache memory includes mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines, locking the first member of the plurality of cache lines creating a locked cache region and an unlocked cache region, remapping the member of the plurality of memory addresses from the first member of the plurality of cache lines onto a second member of the plurality of cache lines within the unlocked cache region, requesting data stored in the main memory, fetching the data from the locked cache region, if available in the locked cache region, fetching the data from the unlocked cache region, if not available in the locked cache region and available in the unlocked cache region, and fetching the data from the main memory, if not available in the locked cache region and not available in the unlocked cache region.
摘要翻译：管理高速缓存存储器中的数据的方法包括将主存储器中的多个存储器地址的成员映射到多条高速缓存行的第一成员上，锁定多条高速缓存行中的第一成员创建锁定高速缓存区域，以及解锁的高速缓存区域，将多个存储器地址的成员从多个高速缓存行的第一成员重新映射到解锁的高速缓存区域内的多个高速缓存行的第二成员上，请求存储在主存储器中的数据，来自锁定的高速缓存区域的数据（如果在锁定的高速缓存区域中可用）从未锁定的高速缓存区域获取数据（如果在锁定高速缓存区域中不可用并且在解锁的高速缓存区域中可用）以及从主存储器获取数据，如果在锁定的高速缓存区域中不可用，并且在解锁的高速缓存区域中不可用。

7. 发明授权

US08244969B2 System including a fine-grained memory and a less-fine-grained memory 有权
标题翻译：系统包括细粒度的内存和较细粒度的内存
公开(公告)号：US08244969B2
公开(公告)日：2012-08-14
申请号：US13149851
申请日：2011-05-31
申请人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
发明人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
IPC分类号： G06F12/00
CPC分类号： G06F12/0284 , G06F12/0802 , G06F12/0806 , G06F2212/1044 , G06F2212/2022 , G06F2212/2542 , G06F2212/401 , Y02D10/13
摘要： A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
摘要翻译：数据处理系统包括一个或多个节点，每个节点包括存储器子系统。子系统包括细粒度的存储器和较细粒度的（例如基于页面的）存储器。细粒度的内存可选地用作基于页面的存储器的缓存和/或写入缓冲器。在系统上执行的软件使用节点地址空间，其能够访问所有节点的基于页面的存储器。每个节点可选地为该空间的至少一部分提供ACID存储器属性。在空间的至少一部分中，存储器元素被映射到基于页的存储器中的位置。在各种实施例中，一些元素被压缩，压缩的元素被打包成页面，页面被写入基于页面的存储器中的可用位置，并且映射维持一些元素和位置之间的关联。

8. 发明申请

US20110289263A1 SYSTEM INCLUDING A FINE-GRAINED MEMORY AND A LESS-FINE-GRAINED MEMORY 有权
标题翻译：系统包括细粒度的记忆和一个细微的记忆
公开(公告)号：US20110289263A1
公开(公告)日：2011-11-24
申请号：US13149851
申请日：2011-05-31
申请人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
发明人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
IPC分类号： G06F12/02
CPC分类号： G06F12/0284 , G06F12/0802 , G06F12/0806 , G06F2212/1044 , G06F2212/2022 , G06F2212/2542 , G06F2212/401 , Y02D10/13
摘要： A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
摘要翻译：数据处理系统包括一个或多个节点，每个节点包括存储器子系统。该子系统包括细粒度的存储器和不太细粒度的（例如基于页面的）存储器。细粒度的内存可选地用作基于页面的存储器的缓存和/或写入缓冲器。在系统上执行的软件使用节点地址空间，其能够访问所有节点的基于页面的存储器。每个节点可选地为该空间的至少一部分提供ACID存储器属性。在空间的至少一部分中，存储器元素被映射到基于页的存储器中的位置。在各种实施例中，一些元素被压缩，压缩的元素被打包成页面，页面被写入基于页面的存储器中的可用位置，并且映射维持一些元素和位置之间的关联。

9. 发明授权

US07903557B1 Multipathing using multiple endpoint addresses for load balancing in a network 有权
标题翻译：多路径使用多个端点地址进行网络中的负载平衡
公开(公告)号：US07903557B1
公开(公告)日：2011-03-08
申请号：US11525254
申请日：2006-09-20
申请人： Ian G. Colloff , Gregory B. Lindahl , Thomas M. McWilliams
发明人： Ian G. Colloff , Gregory B. Lindahl , Thomas M. McWilliams
IPC分类号： G01R31/08
CPC分类号： H04L47/125
摘要： A method for balancing load on a network by selecting a path based on a load balancing algorithm and assigning one of several pairs of endpoint addresses for a flow based on the path selected. One pair of endpoint addresses corresponds to a first path and another pair of endpoint addresses corresponds to a second path. If the first path is selected, the first pair of endpoint addresses is assigned to the flow. If the second path is selected, the second pair of endpoint addresses is assigned to the flow. In one embodiment, based on the assigned pair of endpoint address, the flow is switched to an endpoint by the selected path.
摘要翻译：一种用于通过基于负载平衡算法选择路径并基于所选择的路径为流分配几对端点地址之一来平衡网络上的负载的方法。一对端点地址对应于第一路径，另一对端点地址对应于第二路径。如果选择了第一个路径，则将第一对端点地址分配给流。如果选择了第二条路径，则将第二对端点地址分配给流。在一个实施例中，基于所分配的端点地址对，通过所选择的路径将流切换到端点。

10. 发明申请

US20080301256A1 SYSTEM INCLUDING A FINE-GRAINED MEMORY AND A LESS-FINE-GRAINED MEMORY 有权
标题翻译：系统包括细粒度的记忆和一个细微的记忆
公开(公告)号：US20080301256A1
公开(公告)日：2008-12-04
申请号：US12130661
申请日：2008-05-30
申请人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
发明人： Thomas M. McWilliams , Earl T. Cohen , James M. Bodwin , Ulrich Bruening
IPC分类号： G06F15/167 , G06F11/28
CPC分类号： G06F12/0284 , G06F12/0802 , G06F12/0806 , G06F2212/1044 , G06F2212/2022 , G06F2212/2542 , G06F2212/401 , Y02D10/13
摘要： A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses n node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
摘要翻译：数据处理系统包括一个或多个节点，每个节点包括存储器子系统。该子系统包括细粒度的存储器和不太细粒度的（例如基于页面的）存储器。细粒度的内存可选地用作基于页面的存储器的缓存和/或写入缓冲器。系统上执行的软件使用n个节点地址空间，可以访问所有节点的基于页面的存储器。每个节点可选地为该空间的至少一部分提供ACID存储器属性。在空间的至少一部分中，存储器元素被映射到基于页的存储器中的位置。在各种实施例中，一些元素被压缩，压缩的元素被打包成页面，页面被写入基于页面的存储器中的可用位置，并且映射维持一些元素和位置之间的关联。

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